专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US08552568B2 Methods for forming three-dimensional memory devices, and related structures 有权
标题翻译：形成三维记忆装置的方法及相关结构
公开(公告)号：US08552568B2
公开(公告)日：2013-10-08
申请号：US13450960
申请日：2012-04-19
申请人： Nishant Sinha , Krishna K. Parat
发明人： Nishant Sinha , Krishna K. Parat
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L27/11551 , H01L27/11524
摘要： Methods of forming semiconductor devices that include one or more arrays of memory devices in a three-dimensional arrangement, such as those that include forming a conductive contact in a dielectric material overlying a memory array, wherein a wafer bonding and cleaving process may be utilized to provide a foundation material for forming another memory array having an active region in electrical contact with the conductive contact. Additionally, the conductive contact may be formed in a donor wafer, which in turn may be bonded to a dielectric material overlying a memory array using another wafer bonding process. Novel semiconductor devices and structures including the same may be formed using such methods.
摘要翻译：形成包括三维布置的一个或多个存储器件阵列的半导体器件的方法，例如包括在覆盖存储器阵列的电介质材料中形成导电接触的方法，其中可利用晶片接合和切割工艺提供用于形成具有与导电触点电接触的有源区的另一个存储器阵列的基础材料。此外，导电接触可以形成在施主晶片中，该施主晶片又可以使用另一晶片接合工艺将其结合到覆盖存储器阵列的电介质材料上。可以使用这种方法形成包括其的新型半导体器件和结构。

92. 发明授权

US08539450B2 Fast and accurate data race detection for concurrent programs with asynchronous calls 有权
标题翻译：快速准确的异步调用并发程序的数据竞争检测
公开(公告)号：US08539450B2
公开(公告)日：2013-09-17
申请号：US12702023
申请日：2010-02-08
申请人： Vineet Kahlon , Nishant Sinha , Yun Zhang , Eric J. Kruus
发明人： Vineet Kahlon , Nishant Sinha , Yun Zhang , Eric J. Kruus
IPC分类号： G06F9/44 , G06F9/45
CPC分类号： G06F8/458 , G06F11/3604
摘要： A system and method for analyzing a concurrent program employ asynchronous function calls for communication and recursion. A control flow graph is constructed based on a context-sensitive pointer analysis, whereupon encountering a function pointer, a points-to set of the function pointer is computed in a context-sensitive fashion to determine a set of potential function calls. The context-sensitive pointer analysis is terminated when no new potential function calls are encountered and where the potential function calls may contribute new data races other than those that exist in the contexts traversed thus far. To decide this, a characterization of pointer aliasing based upon complete update sequences is employed. A set of contexts that may contribute to different data races are enumerated by tracking update sequences for function and lock pointers and pointers that are shared or point to shared memory locations. Data race detection is carried out on the control flow graph.
摘要翻译：用于分析并发程序的系统和方法使用用于通信和递归的异步函数调用。基于上下文敏感指针分析构建控制流程图，随后遇到函数指针，以上下文相关方式计算函数指针的点对集合，以确定一组潜在的函数调用。当没有遇到新的潜在函数调用时，上下文敏感的指针分析被终止，潜在函数调用的潜在函数调用可能会贡献除了迄今为止遍历的上下文中存在的数据之外的新数据种族。为了确定这一点，使用基于完整更新序列的指针混叠的表征。可以通过跟踪共享或指向共享存储器位置的功能和锁定指针和指针的更新序列来枚举可能有助于不同数据竞赛的一组上下文。在控制流程图上进行数据竞赛检测。

93. 发明授权

US08524599B2 Methods of forming at least one conductive element and methods of forming a semiconductor structure 有权
标题翻译：形成至少一个导电元件的方法和形成半导体结构的方法
公开(公告)号：US08524599B2
公开(公告)日：2013-09-03
申请号：US13050725
申请日：2011-03-17
申请人： Sanh D. Tang , Scott E. Sills , Whitney L. West , Rob B. Goodwin , Nishant Sinha
发明人： Sanh D. Tang , Scott E. Sills , Whitney L. West , Rob B. Goodwin , Nishant Sinha
IPC分类号： H01L21/4763
CPC分类号： H01L45/1266 , H01L21/7684 , H01L21/76843 , H01L21/76849 , H01L21/76858 , H01L21/76877 , H01L21/76882 , H01L21/76883 , H01L23/53247 , H01L23/53252 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1608 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.
摘要翻译：形成用于半导体结构和存储单元的导电元件例如互连和电极的方法。所述方法包括在至少一个开口的一部分中形成第一导电材料和第二导电材料，所述第二导电材料包括银，并且执行抛光工艺以用至少一个第一和第二导电材料填充所述至少一个开口。可以进行退火处理以形成银和第一导电材料的混合物或合金。该方法能够形成具有减小的尺寸（例如，小于约20nm）的含银导电元件。所得的导电元件具有所需的电阻率。所述方法可以用于例如形成用于电连接有源器件并形成用于存储器单元的电极的互连。还公开了一种半导体结构和包括这种导电结构的存储单元。

94. 发明授权

US08461060B2 Method and apparatus providing air-gap insulation between adjacent conductors using nanoparticles 有权
标题翻译：使用纳米颗粒在相邻导体之间提供气隙绝缘的方法和装置
公开(公告)号：US08461060B2
公开(公告)日：2013-06-11
申请号：US13616080
申请日：2012-09-14
申请人： Nishant Sinha , Gurtej Sandhu , Neil Greeley , John Smythe
发明人： Nishant Sinha , Gurtej Sandhu , Neil Greeley , John Smythe
IPC分类号： H01L21/31
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating material being a size which prevent the nanoparticles from substantially entering into the air-gap.
摘要翻译：公开了半导体器件及其形成方法，其中至少两个相邻的导体在它们之间具有空隙绝缘体，其被绝缘材料的纳米颗粒覆盖，其尺寸是防止纳米颗粒基本上进入气隙的尺寸。

95. 发明授权

US08446767B2 Memories and their formation 有权
标题翻译：记忆及其形成
公开(公告)号：US08446767B2
公开(公告)日：2013-05-21
申请号：US12829860
申请日：2010-07-02
申请人： Sanh D. Tang , Nishant Sinha
发明人： Sanh D. Tang , Nishant Sinha
IPC分类号： G11C16/04
CPC分类号： H01L27/11551 , G11C16/0483 , H01L27/11578
摘要： Memories and their formation are disclosed. One such memory has first and second memory cells at a first vertical level of the memory, first and second memory cells at a second vertical level of the memory, a first data line is selectively coupled to the first memory cells at the first and second vertical levels, and a second data line over the first data line is selectively coupled to the second memory cells at the first and second vertical levels.
摘要翻译：记忆及其形成被披露。一个这样的存储器具有位于存储器的第一垂直级的第一和第二存储器单元，位于存储器的第二垂直级的第一和第二存储器单元，第一数据线选择性地耦合到第一和第二垂直的第一存储器单元电平和第一数据线上的第二数据线在第一和第二垂直电平选择性地耦合到第二存储器单元。

96. 发明申请

US20130003303A1 MICROELECTRONIC DEVICES WITH IMPROVED HEAT DISSIPATION AND METHODS FOR COOLING MICROELECTRONIC DEVICES 有权
标题翻译：具有改进的散热装置的微电子装置和用于冷却微电子装置的方法
公开(公告)号：US20130003303A1
公开(公告)日：2013-01-03
申请号：US13612337
申请日：2012-09-12
申请人： Joseph T. Lindgren , Warren M. Farnworth , William M. Hiatt , Nishant Sinha
发明人： Joseph T. Lindgren , Warren M. Farnworth , William M. Hiatt , Nishant Sinha
IPC分类号： H05K7/20
CPC分类号： H01L23/367 , H01L23/427 , H01L24/31 , H01L2224/16 , H01L2924/00014 , H01L2924/01033 , H01L2924/014 , H01L2924/10158 , H01L2924/19041 , H01L2224/0401
摘要： Microelectronic devices with improved heat dissipation, methods of making microelectronic devices, and methods of cooling microelectronic devices are disclosed herein. In one embodiment, the microelectronic device includes a microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of active devices at least proximate to the first surface. The second surface has a plurality of heat transfer surface features that increase the surface area of the second surface. In another embodiment, an enclosure having a heat sink and a single or multi-phase thermal conductor can be positioned adjacent to the second surface to transfer heat from the active devices.
摘要翻译：本文公开了具有改善的散热的微电子器件，制造微电子器件的方法以及冷却微电子器件的方法。在一个实施例中，微电子器件包括具有第一表面，与第一表面相对的第二表面的微电子衬底以及至少靠近第一表面的多个有源器件。第二表面具有增加第二表面的表面积的多个传热表面特征。在另一个实施例中，具有散热器和单相或多相热导体的外壳可以邻近第二表面定位以传递来自有源器件的热量。

97. 发明授权

US08317930B2 Rheological fluids for particle removal 有权
标题翻译：用于颗粒去除的流变液
公开(公告)号：US08317930B2
公开(公告)日：2012-11-27
申请号：US13179915
申请日：2011-07-11
申请人： Nishant Sinha
发明人： Nishant Sinha
IPC分类号： B08B3/10
CPC分类号： H01L21/67057 , B08B3/04 , B08B7/00 , H01L21/67086 , Y10T137/206 , Y10T428/24521
摘要： Methods and apparatus for cleaning a substrate (e.g., wafer) in the fabrication of semiconductor devices utilizing electrorheological (ER) and magnetorheological (MR) fluids to remove contaminant residual particles from the substrate surface are provided.
摘要翻译：提供了使用电粘滞性（ER）和磁流变（MR）流体制造半导体器件中的衬底（例如，晶片）以从衬底表面去除污染物残留颗粒的方法和装置。

98. 发明授权

US08232206B2 Methods of forming electrical contacts to structures that are at different heights over a substrate relative to one another 有权
标题翻译：将电触点形成在相对于彼此在衬底上不同高度的结构的方法
公开(公告)号：US08232206B2
公开(公告)日：2012-07-31
申请号：US12751786
申请日：2010-03-31
申请人： Nishant Sinha , Dinesh Chopra , Fred D. Fishburn
发明人： Nishant Sinha , Dinesh Chopra , Fred D. Fishburn
IPC分类号： H01L21/44
CPC分类号： H01L21/288 , H01L21/76805 , H01L21/76816 , H01L21/76879 , H01L23/522 , H01L27/10855 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.
摘要翻译：可以利用无电镀形成与半导体衬底相关的电互连。例如，半导体基板可以形成为具有适合于化学镀的表面的虚拟结构，并且还具有与虚拟结构大致相同的高度的数字线。可以在虚拟结构和数字线上形成层，并且可以通过该层到虚拟结构和数字线的上表面形成开口。随后，导电材料可以在开口内无电镀，以在开口内形成电接触。延伸到虚拟结构的开口可以通过电容器电极，因此形成在该开口内的导电材料可用于与电容器电极形成电接触。

99. 发明授权

US08153019B2 Methods for substantially equalizing rates at which material is removed over an area of a structure or film that includes recesses or crevices 有权
标题翻译：用于在包括凹陷或缝隙的结构或膜的区域上去除材料的速率基本相等的方法
公开(公告)号：US08153019B2
公开(公告)日：2012-04-10
申请号：US11834258
申请日：2007-08-06
申请人： Nishant Sinha , J. Neil Greeley
发明人： Nishant Sinha , J. Neil Greeley
IPC分类号： C09K13/08 , C11D7/28
CPC分类号： C09K13/08 , C09K13/06 , H01L21/31055 , H01L21/31111
摘要： Methods for preventing isotropic removal of materials at corners formed by seams, keyholes, and other anomalies in films or other structures include use of etch blockers to cover or coat such corners. This covering or coating prevents exposure of the corners to isotropic etch solutions and cleaning solutions and, thus, prevents higher material removal rates at the corners than at smoother areas of the structure or film from which material is removed. Solutions, including wet etchants and cleaning solutions, that include at least one type of etch blocker are also disclosed, as are systems for preventing higher rates of material removal at corners formed by seams, crevices, or recesses in a film or other structure. Semiconductor device structures in which etch blockers are located so as to prevent isotropic etchants from removing material from corners of seams, crevices, or recesses in a surface of a film or other structure at undesirably high rates are also disclosed.
摘要翻译：在膜或其他结构中由接缝，键孔和其它异常形成的角部处的各向同性物质的各向同性除去方法包括使用蚀刻阻挡剂来覆盖或涂覆这些角。这种覆盖物或涂层防止角部暴露于各向同性蚀刻溶液和清洁溶液，并且因此防止在角质层处更高的材料去除速率，而不是从其中去除材料的结构或膜的更光滑的区域。还公开了包括至少一种类型的蚀刻阻挡剂的解决方案，包括湿蚀刻剂和清洁溶液，以及用于防止在膜或其它结构中由接缝，缝隙或凹陷形成的拐角处更高速率的材料去除的系统。还公开了其中蚀刻阻挡剂被定位以防止各向同性蚀刻剂从不期望的高速率的膜或其它结构的表面中的接缝，裂缝或凹陷的角落移除材料的半导体器件结构。

100. 发明授权

US08148263B2 Methods for forming conductive vias in semiconductor device components 有权
标题翻译：在半导体器件部件中形成导电通孔的方法
公开(公告)号：US08148263B2
公开(公告)日：2012-04-03
申请号：US12648864
申请日：2009-12-29
申请人： Nishant Sinha
发明人： Nishant Sinha
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L23/49827 , H01L21/76898 , H01L23/481 , H01L2224/02372 , H01L2224/0557 , H01L2924/0002 , H01L2924/00
摘要： A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the substrate so as to extend only partially through the substrate. A barrier layer, such as an insulative layer, may be formed on surfaces of each hole. Surfaces within each hole may be coated with a seed layer, which facilitates adhesion of conductive material within each hole. Conductive material is introduced into each hole. Introduction of the conductive material may be effected by deposition or plating. Alternatively, conductive material in the form of solder may be introduced into each hole.
摘要翻译：在半导体器件部件的衬底中形成导电通孔的方法包括在衬底中形成一个或多个孔或孔或空腔，以便仅部分延伸穿过衬底。可以在每个孔的表面上形成诸如绝缘层的阻挡层。每个孔中的表面可以涂覆有种子层，这有助于在每个孔内粘附导电材料。将导电材料引入每个孔中。导电材料的引入可以通过沉积或电镀来实现。或者，可以将每种孔中引入焊料形式的导电材料。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式