专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US07228109B2 DC offset reduction in radio-frequency apparatus and associated methods 有权
标题翻译：射频设备的DC偏移减少和相关方法
公开(公告)号：US07228109B2
公开(公告)日：2007-06-05
申请号：US10074676
申请日：2002-02-12
申请人： Tod Paulus , Donald A. Kerth , Richard T. Behrens , Jeffrey W. Scott , G. Diwakar Vishakhadatta , G. Tyson Tuttle , Vishnu S. Srinivasan
发明人： Tod Paulus , Donald A. Kerth , Richard T. Behrens , Jeffrey W. Scott , G. Diwakar Vishakhadatta , G. Tyson Tuttle , Vishnu S. Srinivasan
IPC分类号： H04B1/40
CPC分类号： H04L25/061 , H04B1/0003 , H04B1/28 , H04B1/406 , H04B15/02 , H04B15/04 , H04B2215/064
摘要： A radio-frequency receiver circuitry includes a down-converter circuitry, an analog-to-digital converter circuitry, and a DC offset reduction circuitry. The down-converter circuitry accepts a received radio-frequency signal and processes the radio-frequency signal to provide an in-phase down-converted signal and a quadrature down-converted signal to the analog-to-digital converter circuitry. The analog-to-digital converter circuitry converts the in-phase and quadrature down-converted signals to an in-phase digital output signal and a quadrature digital output signal, respectively. The DC offset reduction circuitry couples to the analog-to-digital converter circuitry, and tends to reduce a DC offset transmitted to the in-phase and quadrature digital output signals.
摘要翻译：射频接收器电路包括下变频器电路，模数转换器电路和DC偏移减小电路。下变换器电路接收接收的射频信号并处理射频信号以向模数转换器电路提供同相下变频信号和正交下变频信号。模数转换器电路将同相和正交下变频信号分别转换为同相数字输出信号和正交数字输出信号。 DC偏移降低电路耦合到模数转换器电路，并且倾向于减少传输到同相和正交数字输出信号的DC偏移。

92. 发明授权

US07158574B2 Digital interface in radio-frequency apparatus and associated methods 有权
标题翻译：射频设备数字接口及相关方法
公开(公告)号：US07158574B2
公开(公告)日：2007-01-02
申请号：US09821340
申请日：2001-03-29
申请人： G. Diwakar Vishakhadatta , Jeffrey W. Scott , G. Tyson Tuttle , Vishnu Shankar Srinivasan , Aslamali A. Rafi
发明人： G. Diwakar Vishakhadatta , Jeffrey W. Scott , G. Tyson Tuttle , Vishnu Shankar Srinivasan , Aslamali A. Rafi
IPC分类号： H04L27/00 , H04B1/38
CPC分类号： H04B1/0003 , H04B1/28 , H04B1/406 , H04B15/02
摘要： Radio-frequency (RF) apparatus includes receiver analog circuitry that receives an RF signal and provides at least one digital signal to receiver digital circuitry that functions in cooperation with the receiver analog circuitry. The interface between the receiver analog circuitry and the receiver digital circuitry includes configurable signal lines that function as a serial interface, or as a data and clock signal interface, depending on the state of a control signal.
摘要翻译：射频（RF）设备包括接收模拟电路，其接收RF信号并且向与接收机模拟电路协作起作用的接收机数字电路提供至少一个数字信号。接收器模拟电路和接收机数字电路之间的接口包括用作串行接口的可配置信号线，或者根据控制信号的状态作为数据和时钟信号接口。

93. 发明授权

US07024221B2 Notch filter for DC offset reduction in radio-frequency apparatus and associated methods 有权
公开(公告)号：US07024221B2
公开(公告)日：2006-04-04
申请号：US10075099
申请日：2002-02-12
申请人： Tod Paulus , Richard T. Behrens , Vishnu S. Srinivasan , Mark S. Spurbeck , Donald A. Kerth , Jeffrey W. Scott , G. Tyson Tuttle , G. Diwakar Vishakhadatta
发明人： Tod Paulus , Richard T. Behrens , Vishnu S. Srinivasan , Mark S. Spurbeck , Donald A. Kerth , Jeffrey W. Scott , G. Tyson Tuttle , G. Diwakar Vishakhadatta
IPC分类号： H04B1/38 , H04M1/00
CPC分类号： H04B1/0003 , H04B1/28 , H04B1/406 , H04B15/02 , H04B15/04 , H04B2215/064
摘要： A radio-frequency (RF) receiver includes a receiver analog circuitry and a receiver digital circuitry coupled together. The receiver analog circuitry receives an RF signal. The receiver analog circuitry processes the received RF signal and generates a digital signal that it provides to the receiver digital circuitry. The receiver digital circuitry includes a digital down-converter circuitry that mixes the digital signal provided by a receiver analog circuitry with a digital intermediate frequency (IF) local oscillator signal to generate a digital down-converted signal. The receiver digital circuitry also includes a digital filter circuitry that filters the digital down-converted signal to generate a filtered digital signal. The digital filter circuitry provides a notch at a frequency that corresponds to a residual DC offset of the receiver analog circuitry.

94. 发明授权

US07007154B2 Method and apparatus for interfacing a processor to a coprocessor 有权
公开(公告)号：US07007154B2
公开(公告)日：2006-02-28
申请号：US10007836
申请日：2001-11-05
申请人： William C. Moyer , John Arends , Jeffrey W. Scott
发明人： William C. Moyer , John Arends , Jeffrey W. Scott
IPC分类号： G06F15/00
CPC分类号： G06F9/3012 , G06F9/30116 , G06F9/3861 , G06F9/3879 , G06F9/3881
摘要： A processor (12) to coprocessor (14) interface supporting multiple coprocessors (14, 16) utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor (12) and coprocessor (14) on a bi-directional shared bus (28) either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus (28) is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.

95. 发明授权

US06882673B1 Mirror structure for reducing the effect of feedback on a VCSEL 有权
公开(公告)号：US06882673B1
公开(公告)日：2005-04-19
申请号：US10051510
申请日：2002-01-15
申请人： John Wasserbauer , Jeffrey W. Scott
发明人： John Wasserbauer , Jeffrey W. Scott
IPC分类号： H01S3/08 , H01S5/00 , H01S5/183 , H01S5/20 , H01S5/343
CPC分类号： B82Y20/00 , H01S5/18308 , H01S5/18316 , H01S5/18341 , H01S5/18369 , H01S5/18377 , H01S5/2022 , H01S5/2063 , H01S5/3432 , H01S2301/166
摘要： An exemplary embodiment of the present invention integrates an absorbing layer into the emitting mirror of a VCSEL to reduce the reflectivity of the emitting mirror as seen by the feedback optical wave. The absorbing layer may be made of a suitable semiconductor material, such as a GaAs layer in a laser emitting near 850 nm or highly doped p-layer, and may disposed epitaxially in a semiconductor or metamorphic mirror. Alternatively, a metal layer may be disposed in the dielectric portion of a hybrid mirror or all-dielectric mirror.

96. 发明授权

US06865667B2 Data processing system having redirecting circuitry and method therefor 有权
标题翻译：数据处理系统具有重定向电路及其方法
公开(公告)号：US06865667B2
公开(公告)日：2005-03-08
申请号：US09798390
申请日：2001-03-05
申请人： William C. Moyer , Jeffrey W. Scott , John H. Arends
发明人： William C. Moyer , Jeffrey W. Scott , John H. Arends
IPC分类号： G06F9/318 , G06F9/32 , G06F9/445 , G06F9/00
CPC分类号： G06F8/66 , G06F9/3017 , G06F9/30185 , G06F9/328
摘要： Embodiments of the present invention relate generally to data processing systems having redirecting circuitry. For example, one embodiment relates to redirecting program flow in a data processing system having a data processor for executing instructions, and circuitry that redirects program flow by identifying an address corresponding to an instruction provided to the data processor for which program execution should be redirected when the instruction is decoded by the data processor. The circuitry also generates a control field having an offset corresponding to the address and using the control field to determine when program flow should be redirected. The circuitry creates a redirected address value by combining a portion of the control field with a predetermined address. The data processor implements redirection of program flow by utilizing the redirected address value. Embodiments also relate to redirecting data accesses and to redirecting program flow while remaining in a same execution context.
摘要翻译：本发明的实施例一般涉及具有重定向电路的数据处理系统。例如，一个实施例涉及在具有用于执行指令的数据处理器的数据处理系统中的重定向程序流程，以及通过识别与提供给数据处理器的指令对应的地址来重定向程序流的电路，该指令由数据处理器解码。电路还产生具有对应于地址的偏移的控制字段，并且使用控制字段来确定何时将重定向程序流程。电路通过将控制字段的一部分与预定地址组合来创建重定向的地址值。数据处理器通过利用重定向的地址值实现程序流的重定向。实施例还涉及重定向数据访问和重定向程序流，同时保持在相同的执行上下文中。

97. 发明授权

US06505290B1 Method and apparatus for interfacing a processor to a coprocessor 失效
公开(公告)号：US06505290B1
公开(公告)日：2003-01-07
申请号：US08924518
申请日：1997-09-05
申请人： William C. Moyer , John Arends , Jeffrey W. Scott
发明人： William C. Moyer , John Arends , Jeffrey W. Scott
IPC分类号： G06F1500
CPC分类号： G06F9/3012 , G06F9/30116 , G06F9/3861 , G06F9/3879 , G06F9/3881
摘要： A processor (12) to coprocessor (14) interface supporting multiple coprocessors (14, 16) utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor (12) and coprocessor (14) on a bi-directional shared bus (28) either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus (28) is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.

98. 发明授权

US6000029A Method and apparatus for affecting subsequent instruction processing in a data processor 失效
标题翻译：影响数据处理器中后续指令处理的方法和装置
公开(公告)号：US6000029A
公开(公告)日：1999-12-07
申请号：US963321
申请日：1997-11-03
申请人： William C. Moyer , Jeffrey W. Scott
发明人： William C. Moyer , Jeffrey W. Scott
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F9/46 , G06F9/48 , G06F9/52
CPC分类号： G06F9/30094 , G06F9/30079 , G06F9/30087 , G06F9/4812
摘要： A method and apparatus affects subsequent instruction processing in a data processor (10). In one embodiment, a delay interrupt recognition instruction (IDLY4) is executed by data processor (10) to delay or conditionally delay interrupt recognition for a controlled interval, either for a predetermined period of time or for a predetermined number of instructions, so that a read/modify/write sequence of instructions can be performed without dedicated instructions which define the modification operation. The IDLY4 instruction may affect the manner in which subsequent instructions affect a condition bit (38). The condition bit (38) may thus be used to determine if exception processing occurred during the interrupt non-recognition interval after execution of the IDLY4 instruction.
摘要翻译：一种方法和装置影响数据处理器（10）中的后续指令处理。在一个实施例中，延迟中断识别指令（IDLY4）由数据处理器（10）执行以延迟或有条件地延迟中断识别，以控制间隔一段预定的时间段或预定数量的指令，使得可以在没有定义修改操作的专用指令的情况下执行读取/修改/写入指令序列。 IDLY4指令可能会影响后续指令影响条件位（38）的方式。因此，可以使用条件位（38）来确定在执行IDLY4指令之后的中断非识别间隔期间是否发生异常处理。

99. 发明授权

US5594751A Current-apertured vertical cavity laser 失效
标题翻译：电流孔径垂直腔激光器
公开(公告)号：US5594751A
公开(公告)日：1997-01-14
申请号：US494823
申请日：1995-06-26
申请人： Jeffrey W. Scott
发明人： Jeffrey W. Scott
IPC分类号： H01S5/00 , H01S5/042 , H01S5/183 , H01S5/22 , H01S3/19
CPC分类号： H01S5/18333 , H01S2301/166 , H01S5/18311 , H01S5/18316 , H01S5/1833 , H01S5/18358
摘要： A vertical-cavity surface-emitting laser (VCSEL) has an active region, first and second mirror stacks forming a resonant cavity with a radial variation in index forming a transverse optical mode, and a thin insulating slot within the cavity to constrict the current to a diameter less than the beam waist of the optical mode thereby improving device efficiency and preferentially supporting single mode operation. In one embodiment, an insulating slot is formed by etching or selectively oxidizing a thin aluminum-containing semiconductor layer in towards the center of a cylindrical mesa. The slot thickness is sufficiently thin that the large index discontinuity has little effect on the transverse optical-mode pattern. The slot may be placed near an axial standing-wave null to minimize the perturbation of the index discontinuity and allow the use of thicker slots. In a preferred embodiment, the current constriction, formed by the insulating slot, is located on the p-type side of the active region and has a diameter significantly less than the beam waist of the optical mode, thus minimizing outward diffusion of carriers and ensuring single transverse-mode operation of the laser by suppressing spatial hole burning.
摘要翻译：垂直腔表面发射激光器（VCSEL）具有有源区域，形成谐振腔的第一和第二反射镜叠层具有形成横向光学模式的折射率的径向变化，以及腔内的薄绝缘槽，以将电流收缩直径小于光学模式的光束腰部，从而提高器件效率并优先支持单模操作。在一个实施例中，通过蚀刻或选择性地将薄的含铝半导体层朝向圆柱形台面的中心形成绝缘槽。狭缝厚度足够薄，使得大的折射率不连续性对横向光学模式图案几乎没有影响。槽可以放置在轴向驻波零点附近，以最小化指数不连续性的扰动，并允许使用较厚的槽。在优选实施例中，由绝缘槽形成的电流收缩部位于有源区域的p型侧，并且具有明显小于光学模式的光束腰部的直径，从而最小化载体的向外扩散并确保通过抑制空穴燃烧，激光的单横模操作。

100. 发明授权

US5016012A Technique for compensating switched capacitor circuits having gain-setting resistors 失效
标题翻译：用于补偿具有增益设定电阻的开关电容电路的技术
公开(公告)号：US5016012A
公开(公告)日：1991-05-14
申请号：US416888
申请日：1989-10-04
申请人： Jeffrey W. Scott , Thayamkulangara R. Viswanathan
发明人： Jeffrey W. Scott , Thayamkulangara R. Viswanathan
IPC分类号： H03M1/66 , H03H19/00 , H03M1/06 , H03M1/74 , H03M1/80
CPC分类号： H03M1/0604 , H03M1/804
摘要： A technique for compensating for variations in a resistor set overall gain switched-capacitor circuits, such as high accuracy digital-to-analog converters. The variation in overall gain from the desired gain is due to the variation in the total capacitance of the capacitors, compared to the variation in the resistance of the resistor, in the circuit during manufacture. A bias circuit, with two reference voltage outputs, is adapted to have a capacitor and a fixed resistor vary one of the voltage references depending on the capacitance thereof. The voltage difference between the two voltage references varies the overall gain of the switched capacitor circuit to compensate for variations in the overall gain. Also, a switched-capacitor digital-to-analog converter utilizing the above technique is presented.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式