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91. 发明授权

US08426960B2 Wafer level chip scale packaging 有权
标题翻译：晶圆级芯片级封装
公开(公告)号：US08426960B2
公开(公告)日：2013-04-23
申请号：US11963690
申请日：2007-12-21
申请人： Ming Sun , Tao Feng , François Hébert , Yueh-Se Ho
发明人： Ming Sun , Tao Feng , François Hébert , Yueh-Se Ho
IPC分类号： H01L23/48
CPC分类号： H01L21/6835 , H01L21/568 , H01L24/02 , H01L24/11 , H01L24/17 , H01L2221/68354 , H01L2224/0231 , H01L2224/0233 , H01L2224/0239 , H01L2224/0401 , H01L2224/04042 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01072 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/351 , H01L2924/00
摘要： A method for making back-to-front electrical connections in a wafer level chip scale packaging process is disclosed. A wafer containing a plurality of semiconductor chips is mounted on a package substrate. Each semiconductor chip in the plurality includes one or more electrodes on an exposed back side. Scribe lines between two or more adjacent chips on the wafer are removed to form relatively wide gaps. A conductive material is applied to the back side of the semiconductor chips and in the gaps. The conductive material in the gaps between two or more of the chips is then cut through leaving conductive material on the back side and on side walls of the two or more chips. As a result, the conductive material provides an electrical connection from the electrode on the back side of the chip to the front side of the chip.
摘要翻译：公开了一种用于在晶片级芯片级封装工艺中进行背对背电连接的方法。将包含多个半导体芯片的晶片安装在封装基板上。多个半导体芯片包括暴露背面的一个或多个电极。去除晶片上的两个或更多个相邻芯片之间的划痕线以形成较宽的间隙。将导电材料施加到半导体芯片的背面和间隙中。然后通过在两个或更多个芯片的背侧和侧壁上留下导电材料来切割两个或更多个芯片之间的间隙中的导电材料。结果，导电材料提供从芯片的背面上的电极到芯片的前侧的电连接。

92. 发明申请

US20130075746A1 Lateral PNP Bipolar Transistor with Narrow Trench Emitter 有权
标题翻译：具有窄沟槽发射极的横向PNP双极晶体管
公开(公告)号：US20130075746A1
公开(公告)日：2013-03-28
申请号：US13242970
申请日：2011-09-23
申请人： Shekar Mallikarjunaswamy , François Hébert
发明人： Shekar Mallikarjunaswamy , François Hébert
IPC分类号： H01L29/04 , H01L21/331
CPC分类号： H01L29/6625 , H01L21/02532 , H01L21/02595 , H01L21/2254 , H01L21/31111 , H01L21/324 , H01L21/76224 , H01L29/0649 , H01L29/0808 , H01L29/735
摘要： A lateral bipolar transistor includes trench emitter and trench collector regions to form ultra-narrow emitter regions, thereby improving emitter efficiency. The same trench process is used to form the emitter/collector trenches as well as the trench isolation structures so that no additional processing steps are needed to form the trench emitter and collector. In embodiments of the present invention, the trench emitter and trench collector regions may be formed using ion implantation into trenches formed in a semiconductor layer. In other embodiments, the trench emitter and trench collector regions may be formed by out-diffusion of dopants from heavily doped polysilicon filled trenches.
摘要翻译：横向双极晶体管包括沟槽发射极和沟槽集电极区域，以形成超窄的发射极区域，从而提高发射极效率。使用相同的沟槽工艺来形成发射极/集电极沟槽以及沟槽隔离结构，使得不需要额外的处理步骤来形成沟槽发射极和集电极。在本发明的实施例中，可以使用离子注入形成在半导体层中的沟槽中形成沟槽发射极和沟槽集电极区域。在其他实施例中，沟槽发射极和沟槽集电极区域可以通过从重掺杂的多晶硅填充的沟槽中的掺杂剂的扩散而形成。

93. 发明授权

US08302287B2 Method of manufacturing a multilayer inductor 有权
标题翻译：制造多层电感器的方法
公开(公告)号：US08302287B2
公开(公告)日：2012-11-06
申请号：US12891105
申请日：2010-09-27
申请人： Jun Lu , François Hébert
发明人： Jun Lu , François Hébert
IPC分类号： H01F7/06
CPC分类号： H01F17/0013 , H01F27/29 , H01F41/046 , H01L2224/16235 , H01L2924/15311 , Y10T29/4902 , Y10T29/49069 , Y10T29/49073
摘要： A multilayer inductor includes a bottom magnetic layer having an external conductive pattern formed on a bottom surface thereof for connection to a substrate such as a printed circuit board. The bottom external conductive pattern includes signal/power contacts and first and second inductor electrodes. A top magnetic layer includes a top external conductive pattern having signal/power contacts and inductor electrode contacts. An inductor conductive pattern formed on the top surfaces of intermediate magnetic layers disposed between the top and bottom magnetic layers are electrically coupled to each other by means of through holes to form a spiral inductor element.
摘要翻译：多层电感器包括具有形成在其底表面上的外部导电图案的底部磁性层，用于连接到诸如印刷电路板的基板。底部外部导电图案包括信号/电源触点和第一和第二电感器电极。顶部磁性层包括具有信号/功率触点和电感器电极触点的顶部外部导电图案。形成在设置在顶部和底部磁性层之间的中间磁性层的顶表面上的电感器导电图案通过通孔彼此电耦合以形成螺旋形电感器元件。

94. 发明授权

US08283243B2 Bottom anode schottky diode structure and method 有权
标题翻译：底部阳极肖特基二极管的结构和方法
公开(公告)号：US08283243B2
公开(公告)日：2012-10-09
申请号：US13135371
申请日：2011-06-30
申请人： François Hébert
发明人： François Hébert
IPC分类号： H01L21/28
CPC分类号： H01L29/872 , H01L29/402 , H01L29/66143 , H01L29/861 , H01L2924/0002 , H01L2924/00
摘要： This invention discloses a bottom-anode Schottky (BAS) diode that includes an anode electrode disposed on a bottom surface of a semiconductor substrate. The bottom-anode Schottky diode further includes a sinker dopant region disposed at a depth in the semiconductor substrate extending substantially to the anode electrode disposed on the bottom surface of the semiconductor and the sinker dopant region covered by a buried Schottky barrier metal functioning as a Schottky anode. The BAS diode further includes a lateral cathode region extended laterally from a cathode electrode near a top surface of the semiconductor substrate opposite the Schottky barrier metal wherein the lateral cathode region doped with an opposite dopant from the sinker dopant region and interfacing the sinker dopant region whereby a current path is formed from the cathode electrode to the anode electrode through the lateral cathode region and the sinker dopant region in applying a forward bias voltage and the sinker dopant region depleting the cathode region in applying a reverse bias voltage for blocking a leakage current.
摘要翻译：本发明公开了一种底阳极肖特基（BAS）二极管，其包括设置在半导体衬底的底表面上的阳极电极。底阳极肖特基二极管还包括设置在半导体衬底中的深度处的沉降片掺杂剂区域，其基本上延伸到设置在半导体底表面上的阳极电极和由用作肖特基的埋地肖特基势垒金属覆盖的沉降弧掺杂区域阳极。 BAS二极管进一步包括从阴极延伸到靠近半导体衬底的与肖特基势垒金属相对的顶表面的横向阴极区域，其中侧向阴极区域掺杂有与沉淀弧掺杂区域相反的掺杂剂并且与沉降弧掺杂区域接合，由此在施加正偏压时，通过横向阴极区和沉降弧掺杂区形成电流路径，并且在施加用于阻断泄漏电流的反向偏置电压时消耗阴极区的沉降掺杂区。

95. 发明授权

US08217748B2 Compact inductive power electronics package 有权
标题翻译：紧凑感应电力电子封装
公开(公告)号：US08217748B2
公开(公告)日：2012-07-10
申请号：US12397473
申请日：2009-03-04
申请人： Tao Feng , Xiaotian Zhang , François Hébert , Ming Sun
发明人： Tao Feng , Xiaotian Zhang , François Hébert , Ming Sun
IPC分类号： H01F5/00 , H01F27/28 , H01L27/08
CPC分类号： H01L23/495 , H01F3/14 , H01F17/0033 , H01F17/062 , H01F27/2828 , H01F2027/2814 , H01L24/48 , H01L24/49 , H01L2224/05554 , H01L2224/16 , H01L2224/48091 , H01L2224/48465 , H01L2224/49175 , H01L2924/00014 , H01L2924/01019 , H01L2924/14 , H01L2924/181 , H01L2924/30107 , H01L2924/3025 , Y10T29/49073 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00
摘要： An inductive power electronics package is disclosed. It has a circuit substrate with power inductor attached atop. The power inductor has inductor core of closed magnetic loop with an interior window. The closed magnetic loop can include air gap for inductance adjustment. The circuit substrate has bottom half-coil forming elements constituting a bottom half-coil beneath the inductor core. Also provided are top half-coil forming elements interconnected with the bottom half-coil forming elements to form an inductive coil enclosing the inductor core. An inner connection chip can be added in the interior window for interconnecting bottom half-coil forming elements with top half-coil forming elements. An outer connection chip can be added about the inductor core for interconnecting bottom half-coil forming elements with top half-coil forming elements outside the inductor core. A power Integrated Circuit can be attached to the top side of the circuit substrate as well.
摘要翻译：公开了感应电力电子封装。它有一个电路基板，带有功率电感器。功率电感器具有具有内部窗口的闭合磁环的电感器芯。封闭的磁环可以包括用于电感调节的气隙。电路基板具有构成电感器芯下方的下半线圈的底部半线圈形成元件。还提供了与底部半线圈形成元件互连以形成包围电感器芯的感应线圈的顶部半线圈形成元件。内部连接芯片可以添加到内部窗口中，用于将底部半线圈形成元件与顶部半线圈形成元件相互连接。外部连接芯片可以围绕电感器芯添加，用于将底部半线圈形成元件与电感器芯外部的顶部半线圈形成元件互连。功率集成电路也可以连接到电路基板的顶侧。

96. 发明授权

US08193583B2 Monolithic output stage with vertical high-side PMOS and vertical low-side NMOS interconnected using buried metal, structure and method 失效
标题翻译：具有垂直高边PMOS和垂直低端NMOS的单片输出级使用埋入金属互连，结构和方法
公开(公告)号：US08193583B2
公开(公告)日：2012-06-05
申请号：US12717976
申请日：2010-03-05
申请人： François Hébert
发明人： François Hébert
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/336
CPC分类号： H01L21/823885 , H01L27/088 , H01L29/78642
摘要： A voltage converter can include an output circuit having a vertical high-side device and a vertical low-side device which can be formed on a single die (i.e. a “PowerDie”). The high side device can be a PMOS transistor, while the low side device can be an NMOS transistor. The source of the PMOS transistor and the source of the NMOS transistor can be formed from the same metal structure, with the source of the high side device electrically connected to VIN and the source of the low side device electrically connected to ground. A drain of the high side PMOS transistor can be electrically shorted to the drain of the low side NMOS transistor during device operation using a metal layer which is interposed between the transistors and a semiconductor substrate.
摘要翻译：电压转换器可以包括具有可以形成在单个管芯（即“PowerDie”）上的垂直高侧器件和垂直低侧器件的输出电路。高侧器件可以是PMOS晶体管，而低边器件可以是NMOS晶体管。 PMOS晶体管的源极和NMOS晶体管的源极可以由相同的金属结构形成，高边器件的源极电连接到VIN，低端器件的源极电连接到地。在器件操作期间，使用介于晶体管和半导体衬底之间的金属层，高侧PMOS晶体管的漏极可以与低侧NMOS晶体管的漏极电短路。

97. 发明申请

US20120032244A1 Compact Semiconductor Package with Integrated Bypass Capacitor 有权
标题翻译：集成旁路电容的紧凑型半导体封装
公开(公告)号：US20120032244A1
公开(公告)日：2012-02-09
申请号：US13273546
申请日：2011-10-14
申请人： François Hébert , Kai Liu
发明人： François Hébert , Kai Liu
IPC分类号： H01L29/94
CPC分类号： H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L23/49589 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L2224/37011 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/48247 , H01L2224/48465 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/30107 , H01L2924/3011 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/37099 , H01L2224/84
摘要： A top-side cooled compact semiconductor package with integrated bypass capacitor is disclosed. The top-side cooled compact semiconductor package includes a circuit substrate with terminal leads, numerous semiconductor dies bonded atop the circuit substrate, numerous elevation-adaptive interconnection plates for bonding and interconnecting top contact areas of the semiconductor dies with the circuit substrate, a first member of the elevation-adaptive interconnection plates has a first flat-top area and a second member of the elevation-adaptive interconnection plates has a second flat-top area in level with the first flat-top area, a bypass capacitor, having two capacitor terminals located at its ends, stacked atop the two interconnection plate members while being bonded thereto via the first flat-top area and the second flat-top area for a reduced interconnection parasitic impedance.
摘要翻译：公开了具有集成旁路电容器的顶侧冷却紧凑型半导体封装。顶侧冷却的紧凑型半导体封装包括具有端子引线的电路基板，接合在电路基板顶上的多个半导体管芯，用于将半导体管芯的顶部接触区域与电路基板接合和互连的许多仰角自适应互连板，第一构件所述高度自适应互连板具有第一平顶区域，并且所述仰角自适应互连板的第二构件具有与所述第一平顶区域平齐的第二平顶区域，具有两个电容器端子的旁路电容器位于其端部，并且通过第一平顶部区域和第二平顶部区域结合到两个互连板构件的顶部，以减少互连寄生阻抗。

98. 发明申请

US20120028426A1 Inverted-trench grounded-source FET structure using conductive substrates, with highly doped substrates 有权
公开(公告)号：US20120028426A1
公开(公告)日：2012-02-02
申请号：US13200867
申请日：2011-10-04
申请人： François Hébert
发明人： François Hébert
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L29/0865 , H01L29/0878 , H01L29/0886 , H01L29/407 , H01L29/4175 , H01L29/4236 , H01L29/66689 , H01L29/66704 , H01L29/66719 , H01L29/66734 , H01L29/781 , H01L29/7811 , H01L29/7825
摘要： This invention discloses an inverted field-effect-transistor (iT-FET) semiconductor device that includes a source disposed on a bottom and a drain disposed on a top of a semiconductor substrate. The semiconductor power device further comprises a trench-sidewall gate placed on sidewalls at a lower portion of a vertical trench surrounded by a body region encompassing a source region with a low resistivity body-source structure connected to a bottom source electrode and a drain link region disposed on top of said body regions thus constituting a drift region. The drift region is operated with a floating potential said iT-FET device achieving a self-termination.

99. 发明授权

US08062932B2 Compact semiconductor package with integrated bypass capacitor and method 有权
标题翻译：具有集成旁路电容器和方法的紧凑型半导体封装
公开(公告)号：US08062932B2
公开(公告)日：2011-11-22
申请号：US12330381
申请日：2008-12-08
申请人： François Hébert , Kai Liu
发明人： François Hébert , Kai Liu
IPC分类号： H01L21/00 , H01L21/70
CPC分类号： H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L23/49589 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/48 , H01L2224/37011 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/48247 , H01L2224/48465 , H01L2224/73221 , H01L2224/73265 , H01L2224/83801 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/30107 , H01L2924/3011 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/37099 , H01L2224/84
摘要： A top-side cooled compact semiconductor package with integrated bypass capacitor is disclosed. The top-side cooled compact semiconductor package includes a circuit substrate with terminal leads, numerous semiconductor dies bonded atop the circuit substrate, numerous elevation-adaptive interconnection plates for bonding and interconnecting top contact areas of the semiconductor dies with the circuit substrate, a first member of the elevation-adaptive interconnection plates has a first flat-top area and a second member of the elevation-adaptive interconnection plates has a second flat-top area in level with the first flat-top area, a bypass capacitor, having two capacitor terminals located at its ends, stacked atop the two interconnection plate members while being bonded thereto via the first flat-top area and the second flat-top area for a reduced interconnection parasitic impedance.
摘要翻译：公开了具有集成旁路电容器的顶侧冷却紧凑型半导体封装。顶侧冷却的紧凑型半导体封装包括具有端子引线的电路基板，接合在电路基板顶上的多个半导体管芯，用于将半导体管芯的顶部接触区域与电路基板接合和互连的许多仰角自适应互连板，第一构件所述高度自适应互连板具有第一平顶区域，并且所述仰角自适应互连板的第二构件具有与所述第一平顶区域平齐的第二平顶区域，具有两个电容器端子的旁路电容器位于其端部，并且通过第一平顶部区域和第二平顶部区域结合到两个互连板构件的顶部，以减少互连寄生阻抗。

100. 发明授权

US08044486B2 Bottom anode Schottky diode structure 有权
标题翻译：底部阳极肖特基二极管结构
公开(公告)号：US08044486B2
公开(公告)日：2011-10-25
申请号：US12653345
申请日：2009-12-11
申请人： François Hébert
发明人： François Hébert
IPC分类号： H01L27/095 , H01L29/93 , H01L29/861 , H01L31/107
CPC分类号： H01L29/872 , H01L29/402 , H01L29/66143 , H01L29/861 , H01L2924/0002 , H01L2924/00
摘要： This invention discloses a bottom-anode Schottky (BAS) diode that includes an anode electrode disposed on a bottom surface of a semiconductor substrate. The bottom-anode Schottky diode further includes a sinker dopant region disposed at a depth in the semiconductor substrate extending substantially to the anode electrode disposed on the bottom surface of the semiconductor and the sinker dopant region covered by a buried Schottky barrier metal functioning as a Schottky anode. The BAS diode further includes a lateral cathode region extended laterally from a cathode electrode near a top surface of the semiconductor substrate opposite the Schottky barrier metal wherein the lateral cathode region doped with an opposite dopant from the sinker dopant region and interfacing the sinker dopant region whereby a current path is formed from the cathode electrode to the anode electrode through the lateral cathode region and the sinker dopant region in applying a forward bias voltage and the sinker dopant region depleting the cathode region in applying a reverse bias voltage for blocking a leakage current.
摘要翻译：本发明公开了一种底阳极肖特基（BAS）二极管，其包括设置在半导体衬底的底表面上的阳极电极。底阳极肖特基二极管还包括设置在半导体衬底中的深度处的沉降片掺杂剂区域，其基本上延伸到设置在半导体底表面上的阳极电极和由用作肖特基的埋地肖特基势垒金属覆盖的沉降弧掺杂区域阳极。 BAS二极管进一步包括从阴极延伸到靠近半导体衬底的与肖特基势垒金属相对的顶表面的横向阴极区域，其中侧向阴极区域掺杂有与沉降弧掺杂区域相反的掺杂剂，并且与沉淀弧掺杂区域接合，由此在施加正偏压时，通过横向阴极区和沉降弧掺杂区形成电流路径，并且在施加用于阻断泄漏电流的反向偏置电压时消耗阴极区的沉降掺杂区。

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