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91. 发明授权

US6159852A Method of depositing polysilicon, method of fabricating a field effect transistor, method of forming a contact to a substrate, method of forming a capacitor 失效
标题翻译：沉积多晶硅的方法，制造场效应晶体管的方法，与衬底形成接触的方法，形成电容器的方法
公开(公告)号：US6159852A
公开(公告)日：2000-12-12
申请号：US23239
申请日：1998-02-13
申请人： Michael Nuttall , Er-Xuan Ping , Yongjun Jeff Hu
发明人： Michael Nuttall , Er-Xuan Ping , Yongjun Jeff Hu
IPC分类号： C23C16/04 , C23C16/24 , H01L21/285 , H01L21/768 , H01L29/417 , H01L29/78 , H01L21/4763
CPC分类号： H01L29/41783 , C23C16/04 , C23C16/24 , H01L21/28525 , H01L21/28562 , H01L21/76879 , H01L29/41775 , H01L29/7834
摘要： In a method of depositing polysilicon comprises providing a substrate within a chemical vapor deposition reactor, with the substrate having an exposed substantially crystalline region and an exposed substantially amorphous region. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to selectively deposit polysilicon on the crystalline region and not the amorphous region. In another aspect a method of fabricating a field effect transistor on a substrate comprises forming a gate dielectric layer and a gate over semiconductive material. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the source/drain regions and not on amorphous material, and forming elevated source/drains on the doped source/drain regions. In another aspect, a method of forming a contact to a substrate is disclosed. A contact opening is etched through amorphous insulating material over a node location ultimately comprising an outwardly exposed substantially crystalline surface. Within a chemical vapor deposition reactor, a gaseous precursor comprising silicon is provided under conditions effective to selectively deposit polysilicon on the outwardly exposed crystalline node location surface and not on the insulating material.
摘要翻译：在沉积多晶硅的方法中包括在化学气相沉积反应器内提供衬底，其中衬底具有暴露的基本上结晶的区域和暴露的基本非晶区域。包含硅的气体前体在有效选择性地在结晶区域而非非晶区域上沉积多晶硅的条件下进料至化学气相沉积反应器。在另一方面，在衬底上制造场效应晶体管的方法包括形成栅极介电层和半导体材料上的栅极。包含硅的气体前体在有效基本上选择性地在源极/漏极区域上而不是无定形材料上沉积多晶硅并且在掺杂源极/漏极区域上形成升高的源极/漏极的条件下被馈送到化学气相沉积反应器。另一方面，公开了一种形成与基板的接触的方法。接触开口在最终包括向外暴露的基本上结晶的表面的节点位置上通过非晶绝缘材料蚀刻。在化学气相沉积反应器内，在有效选择性地将多晶硅沉积在外露的晶体结点位置表面而不是在绝缘材料上的条件下提供了包含硅的气态前体。

92. 发明授权

US6124164A Method of making integrated capacitor incorporating high K dielectric 有权
标题翻译：制造集成电容器的高K电介质的方法
公开(公告)号：US6124164A
公开(公告)日：2000-09-26
申请号：US156545
申请日：1998-09-17
申请人： Husam N. Al-Shareef , Er-Xuan Ping
发明人： Husam N. Al-Shareef , Er-Xuan Ping
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/8249
CPC分类号： H01L28/55 , H01L28/91 , H01L27/10852 , H01L28/82
摘要： An integrated capacitor is provided, incorporating a high dielectric constant material. In a disclosed method, a high k capacitor dielectric is formed in the shape of a container above a protective layer. After the dielectric is formed, inner and outer electrodes are formed, representing storage and reference electrodes of a memory cell. Contact is separately made through the protective layer from a storage electrode layer, which lines the inner surface of the dielectric, to an underlying polysilicon plug. The contact can be a thin layer lining the interior of the storage electrode layer, or can completely fill the container capacitor. In the latter instance, the contact can form part of the storage electrode and contribute to capacitance of the cell. Volatile dielectric materials can thus be formed prior to the electrodes, avoiding oxidation of the electrodes and underlying polysilicon plug, while also minimizing oxygen depletion through diffusion from the high dielectric constant material.
摘要翻译：提供了一种集成电容器，其包括高介电常数材料。在公开的方法中，高k电容器电介质形成为保护层上方的容器形状。在形成电介质之后，形成表示存储单元的存储和参考电极的内部和外部电极。接触件通过保护层从存储电极层分别制成，该电极层将电介质的内表面排列到下面的多晶硅插塞。接触可以是在存储电极层的内部衬里的薄层，或者可以完全填充容器电容器。在后一种情况下，接触可以形成存储电极的一部分并有助于电池的电容。因此，可以在电极之前形成挥发性介电材料，避免电极和下面的多晶硅插塞的氧化，同时还通过从高介电常数材料的扩散减少氧耗尽。

93. 发明授权

US5937314A Diffusion-enhanced crystallization of amorphous materials to improve surface roughness 失效
公开(公告)号：US5937314A
公开(公告)日：1999-08-10
申请号：US807443
申请日：1997-02-28
申请人： Er-Xuan Ping , Randhir Thakur
发明人： Er-Xuan Ping , Randhir Thakur
IPC分类号： H01L21/00 , H01L21/02 , H01L21/20 , H01L21/8242 , H01L21/84 , H01L21/225
CPC分类号： H01L28/84 , H01L21/2022 , H01L27/1085 , H01L28/90
摘要： Methods of forming a roughened surface through diffusion-enhanced crystallization of an amorphous material are disclosed. In one aspect, conductive hemispherical grain silicon can be formed through dopant diffusion-enhanced crystallization of one or more layers of amorphous silicon. To further enhance uniformity in the formation of the hemispherical grain silicon, the exposed surface of the amorphous silicon can be seeded before crystallization to further enhance uniformity of the surface structures formed in the hemispherical grain silicon.

94. 发明授权

US09023723B2 Method of fabricating a gate-all-around word line for a vertical channel DRAM 有权
标题翻译：制造垂直通道DRAM的全栅字线的方法
公开(公告)号：US09023723B2
公开(公告)日：2015-05-05
申请号：US13986515
申请日：2013-05-09
申请人： Chorng-Ping Chang , Er-Xuan Ping , Judon Tony Pan
发明人： Chorng-Ping Chang , Er-Xuan Ping , Judon Tony Pan
IPC分类号： H01L27/108
CPC分类号： H01L27/10844 , H01L27/10885 , H01L27/10891
摘要： A method of fabricating a self-aligned buried wordline in a structure which contains a self-aligned buried bit line, where the overall structure which makes up a portion of a vertical channel DRAM. The materials and processes used enable self-alignment of elements of the buried wordline during the fabrication process. In addition, the materials and processes used enable for formation of individual DRAM cells which have a buried bit line width which is 16 nm or less and a perpendicular buried wordline width which is 24 nm or less.
摘要翻译：一种在包含自对准掩埋位线的结构中制造自对准掩埋字线的方法，其中构成垂直沟道DRAM的一部分的整体结构。所使用的材料和工艺在制造过程中能够对掩埋字线的元件进行自对准。此外，所使用的材料和工艺能够形成具有16nm或更小的掩埋位线宽度和24nm或更小的垂直掩埋字线宽度的各个DRAM单元。

95. 发明授权

US08895432B2 Method of fabricating a self-aligned buried bit line for a vertical channel DRAM 有权
标题翻译：制造用于垂直沟道DRAM的自对准掩埋位线的方法
公开(公告)号：US08895432B2
公开(公告)日：2014-11-25
申请号：US13986499
申请日：2013-05-08
申请人： Chorng-Ping Chang , Bingxi Wood , Er-Xuan Ping
发明人： Chorng-Ping Chang , Bingxi Wood , Er-Xuan Ping
IPC分类号： H01L21/768 , H01L23/498
CPC分类号： H01L21/76889 , H01L21/743 , H01L23/498 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a self-aligned buried bit line in a structure which makes up a portion of a vertical channel DRAM. The materials and processes used enable self-alignment of elements of the buried bit line during the fabrication process. In addition, the materials and processes used enable for formation of individual DRAM cells which have a buried bit line width which is 16 nm or less.
摘要翻译：在构成垂直通道DRAM的一部分的结构中制造自对准埋入位线的方法。所使用的材料和工艺在制造过程中能够对掩埋位线的元件进行自对准。此外，所使用的材料和工艺能够形成具有16nm或更小的掩埋位线宽度的各个DRAM单元。

96. 发明申请

US20130323920A1 Method of fabricating a gate-all-around word line for a vertical channel dram 有权
标题翻译：一种用于垂直通道的门的全方位字线的制作方法
公开(公告)号：US20130323920A1
公开(公告)日：2013-12-05
申请号：US13986515
申请日：2013-05-09
申请人： Chorng-Ping Chang , Er-Xuan Ping , Judon Tony Pan
发明人： Chorng-Ping Chang , Er-Xuan Ping , Judon Tony Pan
IPC分类号： H01L27/108
CPC分类号： H01L27/10844 , H01L27/10885 , H01L27/10891
摘要： A method of fabricating a self-aligned buried wordline in a structure which contains a self-aligned buried bit line, where the overall structure which makes up a portion of a vertical channel DRAM. The materials and processes used enable self-alignment of elements of the buried wordline during the fabrication process. In addition, the materials and processes used enable for formation of individual DRAM cells which have a buried bit line width which is 16 nm or less and a perpendicular buried wordline width which is 24 nm or less.
摘要翻译：一种在包含自对准掩埋位线的结构中制造自对准掩埋字线的方法，其中构成垂直沟道DRAM的一部分的整体结构。所使用的材料和工艺在制造过程中能够对掩埋字线的元件进行自对准。此外，所使用的材料和工艺能够形成具有16nm或更小的掩埋位线宽度和24nm或更小的垂直掩埋字线宽度的各个DRAM单元。

97. 发明申请

US20120223414A1 METHODS FOR INCREASING BOTTOM ELECTRODE PERFORMANCE IN CARBON-BASED MEMORY DEVICES 审中-公开
标题翻译：在基于碳的存储器件中增加底电极性能的方法
公开(公告)号：US20120223414A1
公开(公告)日：2012-09-06
申请号：US13204772
申请日：2011-08-08
申请人： April D. Schricker , Er-Xuan Ping
发明人： April D. Schricker , Er-Xuan Ping
IPC分类号： H01L29/92 , H01L21/02 , B82Y40/00 , B82Y99/00
CPC分类号： G11C13/025 , B82Y10/00 , G11C2213/35 , G11C2213/71 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/149 , H01L45/1608 , H01L45/1675
摘要： In some aspects, a method of forming a reversible resistance-switching metal-insulator-metal (“MIM”) stack is provided, the method including: forming a first conducting layer comprising a titanium nitride material having between about 50% Ti and about 95% Ti, forming a carbon nano-tube (CNT) material above the first conducting layer, forming a second conducting layer above the CNT material, and etching the first conducting layer, CNT material and second conducting layer to form the MIM stack. Numerous other aspects are provided.
摘要翻译：在一些方面，提供了一种形成可逆电阻切换金属 - 绝缘体 - 金属（“MIM”）堆叠的方法，所述方法包括：形成包含约50％Ti和约95之间的氮化钛材料的第一导电层％Ti，在第一导电层上形成碳纳米管（CNT）材料，在CNT材料之上形成第二导电层，蚀刻第一导电层，CNT材料和第二导电层以形成MIM叠层。提供了许多其他方面。

98. 发明授权

US08023310B2 Nonvolatile memory cell including carbon storage element formed on a silicide layer 有权
标题翻译：包括形成在硅化物层上的碳储存元件的非易失性存储单元
公开(公告)号：US08023310B2
公开(公告)日：2011-09-20
申请号：US12320008
申请日：2009-01-14
申请人： Chu-Chen Fu , Tanmay Kumar , Er-Xuan Ping , Huiwan Xu
发明人： Chu-Chen Fu , Tanmay Kumar , Er-Xuan Ping , Huiwan Xu
IPC分类号： G11C11/00 , G11C11/56 , H01L29/06
CPC分类号： H01L27/101 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/149 , H01L45/1616 , H01L45/1675
摘要： A nonvolatile memory cell includes a storage element, the storage element comprising a carbon material, a steering element located in series with the storage element, and a metal silicide layer located adjacent to the carbon material. A method of making a device includes forming a metal silicide over a silicon layer, forming a carbon layer over the metal silicide layer, forming a barrier layer over the carbon layer, and patterning the carbon layer, the metal silicide layer, and the silicon layer to form an array of pillars.
摘要翻译：非易失性存储单元包括存储元件，所述存储元件包括碳材料，与所述存储元件串联定位的操舵元件和位于所述碳材料附近的金属硅化物层。制造器件的方法包括在硅层上形成金属硅化物，在金属硅化物层上形成碳层，在碳层上形成阻挡层，并对碳层，金属硅化物层和硅层进行构图形成一系列的柱子。

99. 发明申请

US20110210306A1 MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：包含基于碳的存储元件的存储器单元及其形成方法
公开(公告)号：US20110210306A1
公开(公告)日：2011-09-01
申请号：US12714359
申请日：2010-02-26
申请人： Yubao Li , Er-Xuan Ping
发明人： Yubao Li , Er-Xuan Ping
IPC分类号： H01L45/00 , H01L21/20
CPC分类号： H01L45/04 , H01L27/2409 , H01L27/2481 , H01L45/122 , H01L45/149 , H01L45/1616 , H01L45/1691
摘要： A method of forming a reversible resistance-switching metal-carbon-metal (“MCM”) device is provided, the device including a first conducting layer, a second conducting layer, and a reversible resistance-switching element disposed between the first and second conducting layers, wherein the reversible resistance-switching element includes thermal CVD graphitic material and includes a highly resistive region that favors crack formation. Other aspects are also provided.
摘要翻译：提供一种形成可逆电阻切换金属 - 碳 - 金属（“MCM”）器件的方法，该器件包括第一导电层，第二导电层和设置在第一和第二导电层之间的可逆电阻切换元件层，其中可逆电阻切换元件包括热CVD石墨材料，并且包括有利于裂纹形成的高电阻区域。还提供其他方面。

100. 发明授权

US07989864B2 Methods for enhancing capacitors having roughened features to increase charge-storage capacity 失效
标题翻译：用于增强具有粗糙特征的电容器以增加电荷存储容量的方法
公开(公告)号：US07989864B2
公开(公告)日：2011-08-02
申请号：US12538779
申请日：2009-08-10
申请人： Randhir P. S. Thakur , Garry A. Mercaldi , Michael Nuttall , Shenline Chen , Er-Xuan Ping
发明人： Randhir P. S. Thakur , Garry A. Mercaldi , Michael Nuttall , Shenline Chen , Er-Xuan Ping
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： G11C11/404 , G11C17/16 , H01L21/28568 , H01L21/76888 , H01L27/1085 , H01L27/10852 , H01L27/11502 , H01L27/11507 , H01L28/60 , H01L28/82 , H01L28/84
摘要： Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from an undoped silicon film. If the semiconductor structure is a capacitor, the protrusions help to increase the capacitance of the capacitor. The semiconductor structure also includes a relatively smooth surface abutting the rough surface, wherein the relatively smooth surface is formed from a polycrystalline material.
摘要翻译：讨论了制造半导体结构的结构和方法。半导体结构包括具有由未掺杂硅膜形成的突起的粗糙表面。如果半导体结构是电容器，则突起有助于增加电容器的电容。半导体结构还包括与粗糙表面邻接的相对光滑的表面，其中相对光滑的表面由多晶材料形成。

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