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    • 94. 发明授权
    • Semiconductor integrated circuit
    • 半导体集成电路
    • US07940083B2
    • 2011-05-10
    • US12177684
    • 2008-07-22
    • Keitaro Yamashita
    • Keitaro Yamashita
    • H03K19/0175H03K19/094H03L5/00
    • H03K19/00384H03K19/018521H03K19/018528
    • A semiconductor integrated circuit capable of maintaining characteristics of transistors in a circuit including a plurality of cascade connected transistors. The circuit includes an inverter which has a series connection of P-MOS transistors and a pair of N-MOS transistors. The P-MOS transistor is connected to a high potential source VH and the N-MOS transistor is connected to a low potential source VL. The gate of each MOS transistor is connected to an input signal line. The inverter circuit further includes a P-MOS transistor connected between a node and input signal line, and an N-MOS transistor connected between a node of the N-MOS transistors and the input signal line. The gates of the P-MOS transistor and the N-MOS transistor are connected to an output signal line of the inverter circuit.
    • 一种半导体集成电路,其能够维持包括多个级联连接的晶体管的电路中的晶体管的特性。 电路包括具有P-MOS晶体管和一对N-MOS晶体管的串联连接的反相器。 P-MOS晶体管连接到高电位源VH,并且N-MOS晶体管连接到低电位源VL。 每个MOS晶体管的栅极连接到输入信号线。 逆变器电路还包括连接在节点和输入信号线之间的P-MOS晶体管,以及连接在N-MOS晶体管的节点和输入信号线之间的N-MOS晶体管。 P-MOS晶体管和N-MOS晶体管的栅极连接到逆变器电路的输出信号线。
    • 95. 发明授权
    • Matrix addressing circuitry and liquid crystal display device using the same
    • 矩阵寻址电路和使用其的液晶显示装置
    • US07928948B2
    • 2011-04-19
    • US11659866
    • 2005-08-11
    • Shuji HaginoHidetoshi WatanabeAkihiro IwatsuKeitaro Yamashita
    • Shuji HaginoHidetoshi WatanabeAkihiro IwatsuKeitaro Yamashita
    • G09G3/36
    • G09G3/3674G09G3/3614G09G3/3648G09G2310/0213G09G2310/0224G09G2320/0209G09G2320/0233G09G2330/021
    • The invention aims at preventing an occurrence of artefacts while reducing power consumption. A matrix addressing method for alternately driving pixels. The frame period of the images is formed by successively sequencing on a time series a plurality of block periods, the block periods each being composed of a first half block being a period for successively sequencing on a time series application timings of the pixel voltages for one or more row electrodes to be provided with one polarity, the second half block being a period for successively sequencing on a time series application timings of the pixel voltages for one or more row electrodes to be provided with the other polarity. Ones of even-numbered row electrodes and odd-numbered row electrodes in arrangement order on the display screen are selected in the first half block. The others spatially adjoining the ones are selected in the second half block. A row electrode selecting order in the first half block and a row electrode selecting order in the second half block during one frame period are made differed from orders in the corresponding half blocks during the other frame period, respectively, so as to mitigate block-period-base visual artefact.
    • 本发明的目的是在减少功耗的同时防止伪影的发生。 用于交替驱动像素的矩阵寻址方法。 图像的帧周期通过在多个块周期的时间序列上连续排序形成,每个块周期由作为用于对一个像素电压的时间序列应用定时的连续排序的前半部分组成的第一半块组成 或更多的行电极被设置为一个极性,第二半块是用于对要被提供有另一极性的一个或多个行电极的像素电压的时间序列应用定时连续排序的周期。 在第一半块中选择偶数行电极和奇数行电极在显示屏上的排列顺序。 在下半部分中选择与空间相邻的那些。 在一个帧周期期间,前半个块中的行电极选择顺序和第二半块中的行电极选择顺序分别与在另一个帧周期期间的对应的半块中的阶数不同,以便减轻块周期 -base视觉伪影。
    • 97. 发明申请
    • MINIATURIZED DEMULTIPLEXER AND ELECTRONIC DEVICE USING SAME
    • 使用相同的微型化解复用器和电子器件
    • US20090273388A1
    • 2009-11-05
    • US12404112
    • 2009-03-13
    • Keitaro Yamashita
    • Keitaro Yamashita
    • H03K17/62
    • H03K17/693G09G3/3648G09G3/3688G09G2300/0828G09G2300/0842G09G2310/0297H03K17/007
    • A demultiplexer includes an input terminal for providing an input signal, a plurality of output terminals for outputting the input signal, and a switching circuit coupled among the input terminal and the plurality of output terminals, and outputting the input signal selectively from the plurality of output terminals according to a plurality of control signals provided to a plurality of control terminals. For miniaturizing the demultiplexer, the switching circuit includes one or more switch elements connected between the input terminal and each of the output terminals in series, wherein at least two of the switch elements coupled to different output terminals are simultaneously switched in response to one control signal from the plurality of control terminals.
    • 解复用器包括用于提供输入信号的输入端子,用于输出输入信号的多个输出端子以及耦合在输入端子和多个输出端子之间的开关电路,并且从多个输出端选择性地输出输入信号 终端根据提供给多个控制终端的多个控制信号。 为了使多路分解器小型化,开关电路包括串联连接在输入端和每个输出端之间的一个或多个开关元件,其中响应一个控制信号同时切换耦合到不同输出端的至少两个开关元件 从多个控制终端。
    • 98. 发明申请
    • DRIVE CIRCUIT
    • 驱动电路
    • US20090160842A1
    • 2009-06-25
    • US12332751
    • 2008-12-11
    • Keitaro Yamashita
    • Keitaro Yamashita
    • G06F3/038
    • G09G3/3677
    • A drive circuit is disclosed. The drive circuit includes a first p-typed thin film transistor (PTFT), a second PTFT, a first n-typed thin film transistor (NTFT), a second NTFT and a capacitor. The drain of the first PTFT is coupled to a first electrical line, and the gate thereof is coupled to a first clock line. The drain of the second PTFT is coupled to a second clock line, and the source thereof is coupled to an output. The source of the first NTFT is coupled to a second electrical line, and the gate thereof is couple to an output of a preceding drive circuit. The source of the second NTFT is couple to a third electrical line, the gate thereof is coupled to a third clock line, and the drain thereof is coupled to the output. The capacitor has one end coupled to the second electrical line, while the other end is coupled to the source of the first PTFT, the drain of the first NTFT and the gate of the second PTFT.
    • 公开了一种驱动电路。 驱动电路包括第一p型薄膜晶体管(PTFT),第二PTFT,第一n型薄膜晶体管(NTFT),第二NTFT和电容器。 第一PTFT的漏极耦合到第一电线,并且其栅极耦合到第一时钟线。 第二PTFT的漏极耦合到第二时钟线,并且其源极耦合到输出端。 第一NTFT的源极耦合到第二电线,并且其栅极耦合到先前的驱动电路的输出端。 第二NTFT的源耦合到第三电线,其栅极耦合到第三时钟线,并且其漏极耦合到输出端。 电容器具有耦合到第二电线的一端,而另一端耦合到第一PTFT的源极,第一NTFT的漏极和第二PTFT的栅极。