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91. 发明授权

US08332552B2 Supporting multiple high bandwidth I/O controllers on a single chip 有权
标题翻译：在单个芯片上支持多个高带宽I / O控制器
公开(公告)号：US08332552B2
公开(公告)日：2012-12-11
申请号：US12270569
申请日：2008-11-13
申请人： Ravi K. Arimilli , Claude Basso , Jean L. Calvignac , Daniel M. Dreps , Edward J. Seminaro
发明人： Ravi K. Arimilli , Claude Basso , Jean L. Calvignac , Daniel M. Dreps , Edward J. Seminaro
IPC分类号： G06F3/00 , G06F13/12 , G06F13/00 , G06F13/42 , G06F15/76 , G06F9/44 , H04L12/28 , H04L12/50 , H03K19/173 , H01L25/00
CPC分类号： G06F13/385
摘要： An integrated processor design includes physical interface macros supporting heterogeneous electrical properties. The processor design comprises a plurality of processing cores and a plurality of physical interfaces to connect to a memory interface, a peripheral component interconnect express (PCI Express or PCIe) interface for input/output, an Ethernet interface for network communication, and/or a serial attached SCSI (SAS) interface for storage. Each physical interface may be programmatically connected to a selected interface controller, such as a memory controller, a PCI Express controller, or an Ethernet controller, for example. A plurality of such controllers may be connected to a switch within the processor design, with the switch also being connected to each physical interface macro. Thus, the physical interface macros may be programmatically connected to a subset of the plurality of controllers.
摘要翻译：集成处理器设计包括支持异质电气特性的物理接口宏。处理器设计包括多个处理核心和多个物理接口以连接到存储器接口，用于输入/输出的外围组件互连快速（PCI Express或PCIe）接口，用于网络通信的以太网接口和/或串行连接SCSI（SAS）接口进行存储。每个物理接口可以以编程方式连接到例如存储器控制器，PCI Express控制器或以太网控制器等所选择的接口控制器。多个这样的控制器可以连接到处理器设计中的开关，开关也连接到每个物理接口宏。因此，物理接口宏可以以编程方式连接到多个控制器的子集。

92. 发明申请

US20120204002A1 Providing to a Parser and Processors in a Network Processor Access to an External Coprocessor 有权
标题翻译：提供给网络处理器中的解析器和处理器访问外部协处理器
公开(公告)号：US20120204002A1
公开(公告)日：2012-08-09
申请号：US13365679
申请日：2012-02-03
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： H04L69/12
摘要： A mechanism is provided for sharing a communication used by a parser (parser path) in a network adapter of a network processor for sending requests for a process to be executed by an external coprocessor. The parser path is shared by processors of the network processor (software path) to send requests to the external processor. The mechanism uses for the software path a request mailbox comprising a control address and a data field accessed by MMIO for sending two types of messages, one message type to read or write resources and one message type to trigger an external process in the coprocessor and a response mailbox for receiving response from the external coprocessor comprising a data field and a flag field. The other processors of the network poll the flag until set and get the coprocessor result in the data field.
摘要翻译：提供了一种用于共享由网络处理器的网络适配器中的解析器（解析器路径）使用的通信的机制，用于发送对要由外部协处理器执行的进程的请求。解析器路径由网络处理器（软件路径）的处理器共享，以将请求发送到外部处理器。该机制用于软件路径，包括由MMIO访问的控制地址和数据字段的请求邮箱，用于发送两种类型的消息，一种用于读取或写入资源的消息类型和一个消息类型以触发协处理器中的外部进程，用于从包括数据字段和标志字段的外部协处理器接收响应的响应邮箱。网络的其他处理器轮询该标志直到设置，并获得协处理器结果的数据字段。

93. 发明授权

US08239524B2 Techniques for dynamically assigning jobs to processors in a cluster based on processor workload 有权
标题翻译：基于处理器工作负载将作业动态分配到集群中的处理器的技术
公开(公告)号：US08239524B2
公开(公告)日：2012-08-07
申请号：US12336256
申请日：2008-12-16
申请人： Lakshminarayana Baba Arimilli , Ravi Kumar Arimilli , Claude Basso , Jean L. Calvignac
发明人： Lakshminarayana Baba Arimilli , Ravi Kumar Arimilli , Claude Basso , Jean L. Calvignac
IPC分类号： G06F15/16 , G06F15/173
CPC分类号： G06F9/5088
摘要： A technique for operating a high performance computing (HPC) cluster includes monitoring workloads of multiple processors included in the HPC cluster. The HPC cluster includes multiple nodes that each include two or more of the multiple processors. One or more threads assigned to one or more of the multiple processors are moved to a different one of the multiple processors based on the workloads of the multiple processors.
摘要翻译：用于操作高性能计算（HPC）集群的技术包括监视包含在HPC集群中的多个处理器的工作负载。 HPC集群包括多个节点，每个节点包含多个处理器中的两个或多个。基于多个处理器的工作负载，分配给多个处理器中的一个或多个的一个或多个线程被移动到多个处理器中的不同处理器。

94. 发明申请

US20120147901A1 COMPACTED BINARY IDENTIFIER GENERATION 审中-公开
标题翻译：压缩二进制识别器生成
公开(公告)号：US20120147901A1
公开(公告)日：2012-06-14
申请号：US13325553
申请日：2011-12-14
申请人： Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken
发明人： Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken
IPC分类号： H04L12/00 , H04J3/00
CPC分类号： H04L69/22 , H04L61/6059 , H04L61/6072
摘要： A technique for generating a compacted binary identifier includes breaking an original binary identifier into equal parts. Each bit of a first one of the parts is exclusive ORed with a start-up value to generate a first result. Each bit of the first result is exclusive ORed with a respective bit of a second one of the parts to generate a second result.
摘要翻译：用于生成压缩二进制标识符的技术包括将原始二进制标识符分解成相等的部分。第一部分的每一位都与启动值进行异或运算以产生第一个结果。第一结果的每一位与该部分的第二个的相应位进行异或运算以产生第二结果。

95. 发明申请

US20110299394A1 Translating Between An Ethernet Protocol And A Converged Enhanced Ethernet Protocol 有权
标题翻译：在以太网协议和融合增强以太网协议之间进行翻译
公开(公告)号：US20110299394A1
公开(公告)日：2011-12-08
申请号：US13150507
申请日：2011-06-01
申请人： Claude Basso , Anil Pothireddy , Christoph Raisch , Saravanan Sethuraman , Vibhor K. Srivastava , Jan-Bernd Themann , Fabrice J. Verplanken
发明人： Claude Basso , Anil Pothireddy , Christoph Raisch , Saravanan Sethuraman , Vibhor K. Srivastava , Jan-Bernd Themann , Fabrice J. Verplanken
IPC分类号： H04L12/26
CPC分类号： H04L47/10 , H04L47/17 , H04L47/30 , H04L47/32 , H04L47/34 , H04L69/08
摘要： Translating between an Ethernet protocol used by a first network component and a Converged Enhanced Ethernet (CEE) protocol used by a second network component, the first and second components coupled through a CEE Converter that translates by: for data flow from the first network component to the second network component: receiving, by the CEE converter, traffic flow definition parameters for a single CEE protocol data flow; calculating, by a credit manager, available buffer space in an outbound frame buffer of the CEE converter for the data flow; communicating, by the credit manager to a CEE credit driver of the first component, the calculated size of the buffer space together with a start sequence number and a flow identifier; and responding, by the CEE credit driver to the CEE converter, with Ethernet frames comprising a private header that includes the flow identifier and a sequence number.
摘要翻译：在由第一网络组件使用的以太网协议和第二网络组件使用的融合增强以太网（CEE）协议之间进行转换，所述第一和第二组件通过CEE转换器耦合，所述CEE转换器通过以下方式耦合：用于从第一网络组件到第二网络组件：由CEE转换器接收单个CEE协议数据流的业务流定义参数; 由信用管理器计算用于数据流的CEE转换器的出站帧缓冲器中的可用缓冲器空间; 由信用管理器将第一组件的CEE信用驱动程序与计算出的缓冲区空间的大小以及起始序列号和流标识符进行通信; 并由CEE信用驱动程序向CEE转换器响应包括包含流标识符和序列号的专用报头的以太网帧。

96. 发明申请

US20110261687A1 Priority Based Flow Control Within a Virtual Distributed Bridge Environment 失效
标题翻译：在虚拟分布式桥梁环境中基于优先级的流量控制
公开(公告)号：US20110261687A1
公开(公告)日：2011-10-27
申请号：US12767543
申请日：2010-04-26
申请人： William J. Armstrong , Claude Basso , Colin B. Verrilli
发明人： William J. Armstrong , Claude Basso , Colin B. Verrilli
IPC分类号： H04L12/24 , H04L12/56
CPC分类号： H04L47/2441 , H04L12/4625 , H04L47/17 , H04L47/266 , H04L47/30 , H04L49/602 , H04L49/70
摘要： Systems and methods to communicate data frames are provided. A particular apparatus may include a first adapter having a first queue configured to store a data frame associated with a first priority. The adapter is configured to generate a first priority pause frame. A distributed virtual bridge may be coupled to the first adapter. The distributed virtual bridge may include an integrated switch router and a first transport layer module configured to provide a frame-based interface to the integrated switch router. The transport layer module may include a first buffer associated with the first priority. A first bridge element of the distributed virtual bridge may be coupled to the first adapter queue and to the first transport layer module. The first bridge element is configured to receive the first priority pause frame from the adapter and to communicate an interrupt signal to the first transport layer module to interrupt delivery of the data frame to the first queue.
摘要翻译：提供了传达数据帧的系统和方法。特定设备可以包括具有被配置为存储与第一优先级相关联的数据帧的第一队列的第一适配器。适配器被配置为生成第一优先级暂停帧。分布式虚拟桥可以耦合到第一适配器。分布式虚拟桥可以包括集成交换路由器和被配置为向集成交换路由器提供基于帧的接口的第一传输层模块。传输层模块可以包括与第一优先级相关联的第一缓冲器。分布式虚拟桥接器的第一桥接元件可以耦合到第一适配器队列和第一传输层模块。第一桥接元件被配置为从适配器接收第一优先级暂停帧，并将中断信号传送到第一传输层模块以中断数据帧到第一队列的传送。

97. 发明申请

US20110158249A1 Assignment Constraint Matrix for Assigning Work From Multiple Sources to Multiple Sinks 失效
标题翻译：分配约束矩阵用于将工作从多个来源分配到多个接收器
公开(公告)号：US20110158249A1
公开(公告)日：2011-06-30
申请号：US12650080
申请日：2009-12-30
申请人： Claude Basso , Jean L. Calvignac , Chih-Jen Chang , Hubertus Franke , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-Jen Chang , Hubertus Franke , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： H04L12/56
CPC分类号： H04L49/9047
摘要： An assignment constraint matrix method and apparatus used in assigning work, such as data packets, from a plurality of sources, such as data queues in a network processing device, to a plurality of sinks, such as processor threads in the network processing device. The assignment constraint matrix is implemented as a plurality of qualifier matrixes adapted to operate simultaneously in parallel. Each of the plurality of qualifier matrixes is adapted to determine sources in a subset of supported sources that are qualified to provide work to a set of sinks based on assignment constraints. The determination of qualified sources may be based sink availability information that may be provided for a set of sinks on a single chip or distributed on multiple chips.
摘要翻译：一种分配约束矩阵方法和装置，用于从网络处理设备中的多个源（诸如网络处理设备中的数据队列）将诸如数据分组的工作分配给诸如网络处理设备中的处理器线程的多个接收器。分配约束矩阵被实现为适于同时并行操作的多个限定符矩阵。多个限定符矩阵中的每一个适于确定被支持的源的子集中的源，所述源被限定为基于分配约束向一组接收器提供工作。合格来源的确定可以是可以在单个芯片上提供用于一组接收器或分布在多个芯片上的接收器可用性信息。

98. 发明授权

US07627701B2 Indicating last data buffer by last bit flag bit 有权
标题翻译：用最后一位标志位指示最后一个数据缓冲区
公开(公告)号：US07627701B2
公开(公告)日：2009-12-01
申请号：US12120419
申请日：2008-05-14
申请人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
IPC分类号： G06F5/00 , G06F15/16
CPC分类号： H04L49/901 , H04L49/103 , H04L49/3018 , H04L49/90 , H04L49/9094
摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.
摘要翻译：提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。每个控制块具有最后一位特征，其是可设置为“一个或”零“的单个位，并且指示何时数据缓冲器具有最后位，当最后一位处于第一位置时，当附加数据缓冲器为被链接到先前的数据缓冲器，指示要发送附加数据缓冲器，并且当没有附加数据缓冲器被链接到先前的数据缓冲器时的第二位置，最后位的位置被传送到指示结束的网络处理器的特定框架。

99. 发明授权

US07577151B2 Method and apparatus for providing a network connection table 失效
标题翻译：提供网络连接表的方法和装置
公开(公告)号：US07577151B2
公开(公告)日：2009-08-18
申请号：US11096571
申请日：2005-04-01
申请人： Claude Basso , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-Jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： H04L12/56
CPC分类号： H04L45/745 , H04L45/00 , H04L45/54
摘要： Method and apparatus for implementing use of a network connection table. In one aspect, searching for network connections includes receiving a packet, and zeroing particular fields of connection information from the packet if a new connection is to be established. The connection information is converted to an address for a location in a direct table using a table access process. The direct table stores patterns and reference information for new and existing connections. The connection information is compared with at least one pattern stored in the direct table at the address to find reference information for the received packet.
摘要翻译：实现网络连接表使用的方法和装置。在一个方面，搜索网络连接包括接收分组，并且如果要建立新的连接，则从分组归零特定的连接信息字段。使用表访问进程将连接信息转换为直接表中的位置的地址。直接表存储新连接和现有连接的模式和参考信息。将连接信息与存储在地址中的直接表中的至少一个模式进行比较，以找到所接收的分组的参考信息。

100. 发明授权

US07573885B1 Alternative routing in PNNI hierarchical networks 失效
标题翻译： PNNI分层网络中的替代路由
公开(公告)号：US07573885B1
公开(公告)日：2009-08-11
申请号：US09633767
申请日：2000-08-07
申请人： Harold Douglas Dykeman , Paolo Michele Scotton , Claude Basso , Philippe Damon
发明人： Harold Douglas Dykeman , Paolo Michele Scotton , Claude Basso , Philippe Damon
IPC分类号： H04L12/28
CPC分类号： H04L45/22 , H04L45/00 , H04L45/04 , H04L45/06 , H04L45/1283 , H04L45/28
摘要： Methods and apparatus are provided for alternative routing of a connection between a source node and a destination node in a PNNI hierarchical network. The alternative routing method comprises responding to a failed connection between said nodes due to a sole-access element of the network structure as seen by the source node, where a said sole-access element is an element which provides sole access to the destination node in said network structure, by: selecting at least one non-sole-access element of the route used by the failed connection in said network structure; identifying an alternative route for the connection in said network structure which does not utilize the at least one selected element; and using the alternative route for establishment of the connection between said nodes.
摘要翻译：提供了用于在PNNI分层网络中的源节点和目的地节点之间的连接的替代路由的方法和装置。替代路由方法包括由于源节点所看到的网络结构的唯一接入元件，响应所述节点之间的故障连接，其中所述唯一接入元件是提供对目的地节点的唯一接入的元素所述网络结构通过：在所述网络结构中选择由所述故障连接使用的路由的至少一个非唯一接入元件; 识别所述网络结构中不利用所述至少一个所选元素的所述连接的替代路由; 并且使用替代路由来建立所述节点之间的连接。

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