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91. 发明申请

US20070128779A1 Semiconductor devices and methods of fabricating the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070128779A1
公开(公告)日：2007-06-07
申请号：US11633403
申请日：2006-12-04
申请人： Chang-Woo Oh , Sung-Hwan Kim , Dong-Gun Park
发明人： Chang-Woo Oh , Sung-Hwan Kim , Dong-Gun Park
IPC分类号： H01L21/84 , H01L31/113
CPC分类号： H01L27/11568 , G11C16/0475 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11573
摘要： Exposed are a semiconductor device and method of fabricating the same. The device includes an insulation film that is disposed between an active pattern and a substrate, which provides various improvements. This structure enhances the efficiency of high integration and offers an advanced structure for semiconductor devices.
摘要翻译：露出的是半导体器件及其制造方法。该装置包括设置在活性图案和基底之间的绝缘膜，其提供各种改进。这种结构提高了高集成度的效率，为半导体器件提供了先进的结构。

92. 发明申请

US20100330761A1 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100330761A1
公开(公告)日：2010-12-30
申请号：US12879308
申请日：2010-09-10
申请人： Chang-Woo Oh , Sung-Hwan Kim , Dong-Gun Park
发明人： Chang-Woo Oh , Sung-Hwan Kim , Dong-Gun Park
IPC分类号： H01L21/336 , H01L21/326
CPC分类号： H01L27/11568 , G11C16/0475 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11573
摘要： Exposed are a semiconductor device and method of fabricating the same. The device includes an insulation film that is disposed between an active pattern and a substrate, which provides various improvements. This structure enhances the efficiency of high integration and offers an advanced structure for semiconductor devices.
摘要翻译：露出的是半导体器件及其制造方法。该装置包括设置在活性图案和基底之间的绝缘膜，其提供各种改进。这种结构提高了高集成度的效率，为半导体器件提供了先进的结构。

93. 发明申请

US20100221876A1 FIELD EFFECT TRANSISTORS WITH VERTICALLY ORIENTED GATE ELECTRODES AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：具有垂直方向栅极电极的场效应晶体管及其制造方法
公开(公告)号：US20100221876A1
公开(公告)日：2010-09-02
申请号：US12754128
申请日：2010-04-05
申请人： Sung-Min Kim , Dong-Gun Park , Dong-Won Kim , Min-Sang Kim , Eun-jung Yun
发明人： Sung-Min Kim , Dong-Gun Park , Dong-Won Kim , Min-Sang Kim , Eun-jung Yun
IPC分类号： H01L21/8234 , H01L21/86
CPC分类号： H01L27/10876 , H01L21/823437 , H01L21/823487 , H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/1203 , H01L29/66621
摘要： In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a peripheral region of the device, and vertically oriented thin body transistor devices in a cell region of the device. In this manner, the advantageous characteristics of each type of device can be applied to appropriate functions of the memory device.
摘要翻译：在半导体器件及其形成方法中，平面型存储器件和垂直取向的薄体器件都形成在公共半导体层上。在存储器件中，例如，希望在器件的外围区域中具有平面型晶体管，并且在器件的单元区域中具有垂直取向的薄体晶体管器件。以这种方式，每种类型的装置的有利特征可以应用于存储装置的适当功能。

94. 发明申请

US20060192249A1 Field effect transistors with vertically oriented gate electrodes and methods for fabricating the same 审中-公开
标题翻译：具有垂直取向栅电极的场效应晶体管及其制造方法
公开(公告)号：US20060192249A1
公开(公告)日：2006-08-31
申请号：US11396488
申请日：2006-04-03
申请人： Sung-Min Kim , Dong-Gun Park , Dong-Won Kim , Min-Sang Kim , Eun-jung Yun
发明人： Sung-Min Kim , Dong-Gun Park , Dong-Won Kim , Min-Sang Kim , Eun-jung Yun
IPC分类号： H01L29/94
CPC分类号： H01L27/10876 , H01L21/823437 , H01L21/823487 , H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/1203 , H01L29/66621
摘要： In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a peripheral region of the device, and vertically oriented thin body transistor devices in a cell region of the device. In this manner, the advantageous characteristics of each type of device can be applied to appropriate functions of the memory device.
摘要翻译：在半导体器件及其形成方法中，平面型存储器件和垂直取向的薄体器件都形成在公共半导体层上。在存储器件中，例如，希望在器件的外围区域中具有平面型晶体管，并且在器件的单元区域中具有垂直取向的薄体晶体管器件。以这种方式，每种类型的装置的有利特征可以应用于存储装置的适当功能。

95. 发明授权

US08168492B2 Field effect transistors with vertically oriented gate electrodes and methods for fabricating the same 有权
标题翻译：具有垂直取向栅电极的场效应晶体管及其制造方法
公开(公告)号：US08168492B2
公开(公告)日：2012-05-01
申请号：US12754128
申请日：2010-04-05
申请人： Sung-Min Kim , Dong-Gun Park , Dong-Won Kim , Min-Sang Kim , Eun-jung Yun
发明人： Sung-Min Kim , Dong-Gun Park , Dong-Won Kim , Min-Sang Kim , Eun-jung Yun
IPC分类号： H01L21/8238
CPC分类号： H01L27/10876 , H01L21/823437 , H01L21/823487 , H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/10894 , H01L27/1203 , H01L29/66621
摘要： In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a peripheral region of the device, and vertically oriented thin body transistor devices in a cell region of the device. In this manner, the advantageous characteristics of each type of device can be applied to appropriate functions of the memory device.
摘要翻译：在半导体器件及其形成方法中，平面型存储器件和垂直取向的薄体器件都形成在公共半导体层上。在存储器件中，例如，希望在器件的外围区域中具有平面型晶体管，并且在器件的单元区域中具有垂直取向的薄体晶体管器件。以这种方式，每种类型的装置的有利特征可以应用于存储装置的适当功能。

96. 发明申请

US20080194065A1 INTEGRATED CIRCUIT DEVICES HAVING AN EPITAXIAL PATTERN WITH A VOID REGION FORMED THEREIN AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：具有形成有空位区域的外延图案的集成电路装置及其形成方法
公开(公告)号：US20080194065A1
公开(公告)日：2008-08-14
申请号：US12107468
申请日：2008-04-22
申请人： Sung-Young Lee , Sung-Min Kim , Dong-Gun Park , Kyoung-Hwan Yeo
发明人： Sung-Young Lee , Sung-Min Kim , Dong-Gun Park , Kyoung-Hwan Yeo
IPC分类号： H01L21/02
CPC分类号： H01L29/66651 , H01L21/76224 , H01L21/76289 , H01L21/764 , H01L29/0649 , H01L29/66795 , H01L29/785 , H01L29/78603 , H01L29/802
摘要： An integrated circuit device includes a substrate. An epitaxial pattern is on the substrate and has a pair of impurity diffusion regions formed therein and a pair of void regions formed therein that are disposed between the pair of impurity diffusion regions and the substrate. Respective ones of the pair of impurity diffusion regions at least partially overlap respective ones of the pair of void regions. A gate electrode is on the epitaxial pattern between respective ones of the pair of impurity diffusion regions.
摘要翻译：集成电路器件包括衬底。外延图案位于基板上，并且在其间形成有一对杂质扩散区域和形成在其中的一对空隙区域，其设置在该对杂质扩散区域和基板之间。该对杂质扩散区域中的各一个至少部分地重叠该对空隙区域中的相应的一个。栅极电极位于一对杂质扩散区域中的各自之间的外延图案上。

97. 发明授权

US07919378B2 Transistor and method of forming the same 有权
标题翻译：晶体管及其形成方法
公开(公告)号：US07919378B2
公开(公告)日：2011-04-05
申请号：US12397176
申请日：2009-03-03
申请人： Jae-Man Yoon , Choong-Ho Lee , Dong-Gun Park , Chul Lee
发明人： Jae-Man Yoon , Choong-Ho Lee , Dong-Gun Park , Chul Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： According to some embodiments of the invention, a fin type transistor includes an active structure integrally formed with a silicon substrate. The active structure includes grooves that form blocking regions under source/drain regions. A gate structure is formed to cross the upper face of the active structure and to cover the exposed side surfaces of the lateral portions of the active structure. An effective channel length of a fin type transistor may be sufficiently ensured so that a short channel effect of the transistor may be prevented and the fin type transistor may have a high breakdown voltage.
摘要翻译：根据本发明的一些实施例，鳍型晶体管包括与硅衬底一体形成的有源结构。活性结构包括在源极/漏极区域下形成阻挡区的沟槽。栅极结构形成为跨越有源结构的上表面并且覆盖有源结构的侧部的暴露的侧表面。可以充分确保翅片型晶体管的有效沟道长度，从而可以防止晶体管的短沟道效应，并且鳍式晶体管可能具有高击穿电压。

98. 发明申请

US20100283094A1 SEMICONDUCTOR DEVICE HAVING VERTICAL TRANSISTOR AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有垂直晶体管的半导体器件及其制造方法
公开(公告)号：US20100283094A1
公开(公告)日：2010-11-11
申请号：US12840599
申请日：2010-07-21
申请人： Bong-Soo Kim , Kang-Yoon Lee , Dong-Gun Park , Jae-Man Yoon , Seong-Goo Kim , Hyeoung-Won Seo
发明人： Bong-Soo Kim , Kang-Yoon Lee , Dong-Gun Park , Jae-Man Yoon , Seong-Goo Kim , Hyeoung-Won Seo
IPC分类号： H01L27/108
CPC分类号： H01L27/10894 , H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.
摘要翻译：提供了具有垂直晶体管的半导体器件及其制造方法。该方法包括制备具有单元区域和外围电路区域的半导体衬底。在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。位线分离沟槽与垂直栅极结构的列方向平行地形成。位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。

99. 发明授权

US07528022B2 Method of forming fin field effect transistor using damascene process 有权
标题翻译：使用镶嵌工艺形成翅片场效应晶体管的方法
公开(公告)号：US07528022B2
公开(公告)日：2009-05-05
申请号：US11112818
申请日：2005-04-21
申请人： Young-Joon Ahn , Dong-Gun Park , Choong-Ho Lee , Hee-Soo Kang
发明人： Young-Joon Ahn , Dong-Gun Park , Choong-Ho Lee , Hee-Soo Kang
IPC分类号： H01L21/8234
CPC分类号： H01L29/7851 , H01L21/26586 , H01L29/66818
摘要： A method of forming a fin transistor using a damascene process is provided. A filling mold insulation pattern is recessed to expose an upper portion of a fin, and a mold layer is formed. The mold layer is patterned to form a groove crossing the fin and exposing a part of the upper portion of the fin. A gate electrode is formed to fill the groove with a gate insulation layer interposed between the fin and the gate electrode, and the mold layer is removed. Impurities are implanted through both sidewalls and a top surface of the upper portion of the fin disposed at opposite sides of a gate electrode to form a source/drain region.
摘要翻译：提供了一种使用镶嵌工艺形成鳍式晶体管的方法。填充模具绝缘图案凹入以暴露翅片的上部，并且形成模具层。图案化模具层以形成与散热片交叉的凹槽并暴露翅片上部的一部分。形成栅电极，用插入翅片和栅电极之间的栅极绝缘层填充凹槽，并且去除模层。通过设置在栅极电极的相对侧的翅片的上侧部分的两个侧壁和顶部表面注入杂质以形成源极/漏极区域。

100. 发明授权

US07465985B2 Non-volatile memory device and methods of forming the same 有权
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：US07465985B2
公开(公告)日：2008-12-16
申请号：US11580086
申请日：2006-10-13
申请人： Byung-Yong Choi , Choong-Ho Lee , Dong-Gun Park
发明人： Byung-Yong Choi , Choong-Ho Lee , Dong-Gun Park
IPC分类号： H01L21/334
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A non-volatile memory device and a method of forming the same are provided. The non-volatile memory device may include a cell isolation pattern and a semiconductor pattern sequentially stacked on a predetermined or given region of a semiconductor substrate, a cell gate line on the semiconductor pattern and on a top surface of the semiconductor substrate on one side of the cell isolation pattern, a multi-layered trap insulation layer between the cell gate line and the semiconductor substrate, and the cell gate line and the semiconductor pattern, a first impurity diffusion layer in the semiconductor substrate on both sides of the cell gate line and a second impurity diffusion layer in the semiconductor pattern on both sides of the cell gate line.
摘要翻译：提供了一种非易失性存储器件及其形成方法。非易失性存储器件可以包括依次层叠在半导体衬底的预定或给定区域上的单元隔离图案和半导体图案，半导体图案上的单元栅极线和半导体衬底的一侧的顶表面上的半导体图案电池隔离图案，单元栅极线和半导体衬底之间的多层陷阱绝缘层，以及单元栅极线和半导体图案，在单元栅极线的两侧的半导体衬底中的第一杂质扩散层和位于单元栅极线两侧的半导体图案中的第二杂质扩散层。

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