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    • 91. 发明授权
    • Method of brewing soy sauce
    • 酿造酱油的方法
    • US07056543B2
    • 2006-06-06
    • US10323625
    • 2002-12-20
    • Masashi KasugaAtsuo YaginumaShizuya OhkuboNobutake NunomuraIsao KimuraMachiko Watanabe
    • Masashi KasugaAtsuo YaginumaShizuya OhkuboNobutake NunomuraIsao KimuraMachiko Watanabe
    • A23B9/28
    • A23L27/50A23L11/09
    • According to the present invention, there is reliably provided a soy sauce having desired ethanol and lactic acid concentrations and a mellow flavor. A method of brewing soy sauce which comprises mixing soy sauce koji into a salt water to prepare a soy sauce moromi mash, adding pre-cultured soy sauce lactic acid bacteria and soy sauce yeast to the moromi mash, performing fermentation and aging of the moromi mash after adding by ordinary techniques, wherein the soy sauce yeast is added to the soy sauce moromi mash within 10 days after mixing such that the cell count of the soy sauce yeast is 10 to 100 fold greater than that of wild yeast already existing in the moromi mash and is 2×105 or less cells/g moromi mash to the soy sauce moromi mash, so that the desired soy sauce is obtained.
    • 根据本发明,可靠地提供具有所需乙醇和乳酸浓度以及醇香味的酱油。 一种酿造酱油的方法,其包括将酱油曲调到盐水中以制备酱油酱油,将预培养的酱油乳酸菌和酱油酵母加入到醪液中,进行发酵和老化的醪液 在通过常规技术添加之后,其中将酱油酵母在混合后10天内加入到酱油酱油中,使得酱油酵母的细胞计数比已经存在于辣椒粉中的野生酵母的细胞计数大10至100倍 糊状,并且是2×10 5个或更少的细胞/ g,使酱油糊状物粉碎,从而获得所需的酱油。
    • 92. 发明授权
    • Method for manufacturing a lateral double-diffused MOS transistor having stable characteristics and equal drift length
    • 用于制造具有稳定特性和相等漂移长度的横向双扩散MOS晶体管的方法
    • US06699740B2
    • 2004-03-02
    • US10075277
    • 2002-02-15
    • Isao Kimura
    • Isao Kimura
    • H01L21336
    • H01L29/7816H01L29/0878H01L29/423H01L29/66681
    • A semiconductor device including a P-type semiconductor layer; an N-type first well on the surface of the semiconductor layer; a P-type second well on the surface of the first well; an N-type source region on the surface of the second well; and an N-type drain region on the surface of the first well and apart from the source region at a specific distance. A gate electrode is formed on the semiconductor layer and extends from the source region to the second well and the first well. An application electrode is arranged apart from the gate electrode on the first well between the second well and the drain region, and extends from the first well to the edge thereof. A P-type first impurity diffusion layer is formed on the surface of the source region and extends to the second well under the source region.
    • 一种包括P型半导体层的半导体器件; 半导体层表面上的N型第一阱; 在第一井的表面上的P型第二井; 在第二井的表面上的N型源区; 以及第一阱表面上的N型漏极区域,并且在特定距离处与源极区域分离。 栅电极形成在半导体层上并从源极区延伸到第二阱和第一阱。 施加电极与位于第二阱和漏极区之间的第一阱上的栅电极分开设置,并从第一阱延伸至其边缘。 在源极区域的表面上形成P型第一杂质扩散层,并在源极区域延伸到第二阱。
    • 96. 发明授权
    • Clock combining circuit
    • 时钟组合电路
    • US5930216A
    • 1999-07-27
    • US842889
    • 1997-04-17
    • Shiro SuzukiIsao KimuraDaniel Wu
    • Shiro SuzukiIsao KimuraDaniel Wu
    • G11B20/14G11B20/10G11B27/30G11B5/76G11B5/09
    • G11B20/10212G11B20/1403G11B27/3027G11B20/1426
    • A clock combining circuit includes a FIFO circuit, a signal combining circuit and a signal selecting circuit. The FIFO circuit accepts, for example, a positive-edge playback signal RDATA0 that has as data the positive edge of a playback signal obtained from recording domains formed in a recording medium, RDATA0 being synchronized with a positive-edge clock signal RCLK0. The FIFO circuit also accepts a negative-edge playback signal RDATA1 that has as data the negative edge of the playback signal, RDATA1 being synchronized with a negative-edge clock signal RCLK1. The FIFO circuit causes RDATA0 and RDATA1 to be synchronized with RCLK0 so as to output a delayed positive-edge playback signal RDATA0D and a delayed negative-edge playback signal RDATA1D. The delayed negative-edge playback signal is delayed by -KT to +LT, where K and L are integers and T is the clock period. The signal combining circuit combines the delayed positive-edge and negative-edge playback signals, and outputs (K+L+1) combined signals. The signal selecting circuit detects marks contained in the playback signal, the marks being independent of the (K+L+1) combined signals, and outputs selected ones of the combined signals based on the detected marks.
    • 时钟组合电路包括FIFO电路,信号组合电路和信号选择电路。 FIFO电路例如接收具有从形成在记录介质中的记录区域获得的重放信号的上升沿作为数据的正边沿重放信号RDATA0,RDATA0与上升沿时钟信号RCLK0同步。 FIFO电路还接受具有作为数据的重放信号的负沿的负边沿重放信号RDATA1,RDATA1与负边沿时钟信号RCLK1同步。 FIFO电路使RDATA0和RDATA1与RCLK0同步,以输出延迟的正边沿重放信号RDATA0D和延迟的负边沿重放信号RDATA1D。 延迟的负边沿重放信号被-KT延迟到+ LT,其中K和L是整数,T是时钟周期。 信号组合电路将延迟的正边沿和负边沿重放信号以及输出(K + L + 1)组合信号相结合。 信号选择电路检测回放信号中包含的标记,标记与(K + L + 1)组合信号无关,并根据检测到的标记输出组合信号中的选定信号。