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91. 发明授权

US07371623B2 Semiconductor device with semiconductor circuit comprising semiconductor units, and method for fabricating it 有权
标题翻译：具有半导体单元的半导体电路的半导体装置及其制造方法
公开(公告)号：US07371623B2
公开(公告)日：2008-05-13
申请号：US10438818
申请日：2003-05-16
申请人： Shunpei Yamazaki , Etsuko Fujimoto , Atsuo Isobe , Toru Takayama , Kunihiko Fukuchi
发明人： Shunpei Yamazaki , Etsuko Fujimoto , Atsuo Isobe , Toru Takayama , Kunihiko Fukuchi
IPC分类号： H01L21/84
CPC分类号： H01L27/1237 , G02F1/13454 , H01L27/1248 , H01L29/458 , H01L29/4908 , H01L29/78645
摘要： The invention is to provide a high-productivity method for fabricating a TFT device having different LDD structures on one and the same substrate, and the TFT device. Specifically, the invention provides a novel TFT structure, and a high-productivity method for fabricating it. A Ta film or a Ta-based film having good heat resistance is used for forming interconnections, and the interconnections are covered with a protective film. The interconnections can be subjected to heat treatment at high temperatures (400 to 700° C.), and, in addition, the protective film serves as an etching stopper. In the peripheral driving circuit portion in the device, TFTs having an LDD structure are disposed in a self-aligned process in which is used side walls 126 and 127; while in the pixel matrix portion therein, TFTs having an LDD structure are disposed in a non-self-aligned process in which is used an insulator 125.
摘要翻译：本发明提供一种用于制造在同一基板上具有不同LDD结构的TFT器件和TFT器件的高生产率方法。具体地说，本发明提供了一种新颖的TFT结构，以及高生产率的制造方法。使用具有良好耐热性的Ta膜或Ta基膜形成互连，并且互连用保护膜覆盖。互连可以在高温（400〜700℃）下进行热处理，另外，保护膜用作蚀刻停止体。在器件的外围驱动电路部分中，具有LDD结构的TFT以自对准工艺设置，其中使用侧壁126和127; 而在其中的像素矩阵部分中，具有LDD结构的TFT被设置在非自对准工艺中，其中使用绝缘体125。

92. 发明申请

US20060246644A1 Semiconductor device and method for manufacturing semiconductor device 有权
标题翻译：半导体装置及半导体装置的制造方法
公开(公告)号：US20060246644A1
公开(公告)日：2006-11-02
申请号：US11410188
申请日：2006-04-25
申请人： Atsuo Isobe , Satoshi Murakami , Shunpei Yamazaki
发明人： Atsuo Isobe , Satoshi Murakami , Shunpei Yamazaki
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L27/1266 , H01L27/1248 , H01L27/1255
摘要： In order to manufacture a highly reliable and compact TFT, it is an object of the present invention to provide a method for manufacturing a semiconductor device for forming a gate electrode, a source wiring and a drain wiring with high reliability, and a semiconductor device. In the method for manufacturing a semiconductor device, a semiconductor film is formed over a substrate having an insulated surface, a gate insulating film is formed over the semiconductor film, a gate electrode is formed over the gate insulating film, and a nitride film is formed over the surface of the gate electrode by nitriding the surface of the gate electrode by using high-density plasma.
摘要翻译：为了制造高度可靠且紧凑的TFT，本发明的目的是提供一种用于制造用于形成具有高可靠性的栅电极，源极布线和漏极布线的半导体器件的方法和半导体器件。在半导体器件的制造方法中，在具有绝缘面的基板上形成半导体膜，在半导体膜上形成栅极绝缘膜，在栅极绝缘膜上形成栅电极，形成氮化膜通过使用高密度等离子体氮化栅电极的表面，在栅电极的表面上。

93. 发明申请

US20060244063A1 Thin film transistor and manufacturing method thereof 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US20060244063A1
公开(公告)日：2006-11-02
申请号：US11410071
申请日：2006-04-25
申请人： Atsuo Isobe , Shunpei Yamazaki
发明人： Atsuo Isobe , Shunpei Yamazaki
IPC分类号： H01L27/12
CPC分类号： H01L27/1266 , H01L27/1214 , H01L27/3244 , H01L29/4908
摘要： The present invention provides a thin film transistor in which a substantial length of a channel is shortened to miniaturize a semiconductor device and a manufacturing method thereof. In addition, the present invention provides a semiconductor device which realizes high-speed operation and high-performance of the semiconductor device and a manufacturing method thereof. Further in addition, it is an object of the present invention to provide a manufacturing method in which a manufacturing process is simplified. The semiconductor device of the present invention has an island-shaped semiconductor film formed over a substrate having an insulating surface and a gate electrode formed over the island-shaped semiconductor film, in which the gate electrode is oxidized its surface by high-density plasma to be slimmed and the substantial length of a channel is shortened.
摘要翻译：本发明提供了一种薄膜晶体管，其中缩短了通道的相当长度以使半导体器件小型化及其制造方法。另外，本发明提供实现半导体器件的高速操作和高性能的半导体器件及其制造方法。另外，本发明的目的在于提供一种制造方法简化的制造方法。本发明的半导体器件具有岛状半导体膜，该岛状半导体膜形成在具有绝缘面的基板上，形成在岛状半导体膜上的栅电极，其中栅电极通过高密度等离子体将其表面氧化成缩小了通道的实际长度。

94. 发明授权

US06822293B2 Semiconductor device equipped with semiconductor circuits composed of semiconductor elements and process for production thereof 有权
标题翻译：配备有由半导体元件构成的半导体电路的半导体装置及其制造方法
公开(公告)号：US06822293B2
公开(公告)日：2004-11-23
申请号：US10338025
申请日：2003-01-08
申请人： Shunpei Yamazaki , Etsuko Fujimoto , Atsuo Isobe , Toru Takayama , Kunihiko Fukuchi
发明人： Shunpei Yamazaki , Etsuko Fujimoto , Atsuo Isobe , Toru Takayama , Kunihiko Fukuchi
IPC分类号： H01L2976
CPC分类号： H01L29/4908 , H01L27/124 , H01L27/1248 , H01L27/1255 , H01L27/1277 , H01L29/42384
摘要： A semiconductor device and a process for production thereof, said semiconductor device having a new electrode structure which has a low resistivity and withstands heat treatment at 400° C. and above. Heat treatment at a high temperature (400-700° C.) is possible because the wiring is made of Ta film or Ta-based film having high heat resistance. This heat treatment permits the gettering of metal element in crystalline silicon film. Since this heat treatment is lower than the temperature which the gate wiring (0.1-5 &mgr;m wide) withstands and the gate wiring is protected with a protective film, the gate wiring retains its low resistance.
摘要翻译：一种半导体器件及其制造方法，所述半导体器件具有新的电极结构，其具有低电阻率并且在400℃及以上的温度下经受热处理。由于布线由具有高耐热性的Ta膜或Ta基膜制成，所以可以在高温（400-700℃）下进行热处理。该热处理允许在晶体硅膜中吸收金属元素。由于该热处理低于栅极布线（宽度为0.1-5μm）耐受并且栅极布线被保护膜保护的温度，所以栅极布线保持其低电阻。

95. 发明授权

US06608357B1 Semiconductor device equipped with semiconductor circuits composed of semiconductor elements and process for production thereof 有权
标题翻译：配备有由半导体元件构成的半导体电路的半导体装置及其制造方法
公开(公告)号：US06608357B1
公开(公告)日：2003-08-19
申请号：US09641768
申请日：2000-08-21
申请人： Shunpei Yamazaki , Etsuko Fujimoto , Atsuo Isobe , Toru Takayama , Kunihiko Fukuchi
发明人： Shunpei Yamazaki , Etsuko Fujimoto , Atsuo Isobe , Toru Takayama , Kunihiko Fukuchi
IPC分类号： H01L2976
CPC分类号： H01L29/4908 , H01L27/124 , H01L27/1248 , H01L27/1255 , H01L27/1277 , H01L29/42384
摘要： A semiconductor device and a process for production thereof, said semiconductor device having a new electrode structure which has a low resistivity and withstands heat treatment at 400° C. and above. Heat treatment at a high temperature (400-700° C.) is possible because the wiring is made of Ta film or Ta-based film having high heat resistance. This heat treatment permits the gettering of metal element in crystalline silicon film. Since this heat treatment is lower than the temperature which the gate wiring (0.1-5 &mgr;m wide) withstands and the gate wiring is protected with a protective film, the gate wiring retains its low resistance.
摘要翻译：一种半导体器件及其制造方法，所述半导体器件具有新的电极结构，其具有低电阻率并且在400℃及以上的温度下经受热处理。由于布线由具有高耐热性的Ta膜或Ta基膜制成，所以可以在高温（400-700℃）下进行热处理。该热处理允许在晶体硅膜中吸收金属元素。由于该热处理低于栅极布线（宽度为0.1-5μm）耐受并且栅极布线被保护膜保护的温度，所以栅极布线保持其低电阻。

96. 发明授权

US6144082A Semiconductor device equipped with semiconductor circuits composed of semiconductor elements and process for production thereof 有权
标题翻译：配备有由半导体元件构成的半导体电路的半导体装置及其制造方法
公开(公告)号：US6144082A
公开(公告)日：2000-11-07
申请号：US353282
申请日：1999-07-14
申请人： Shunpei Yamazaki , Etsuko Fujimoto , Atsuo Isobe , Toru Takayama , Kunihiko Fukuchi
发明人： Shunpei Yamazaki , Etsuko Fujimoto , Atsuo Isobe , Toru Takayama , Kunihiko Fukuchi
IPC分类号： G02F1/136 , G02F1/1368 , H01L21/28 , H01L21/336 , H01L21/77 , H01L21/84 , H01L27/12 , H01L29/423 , H01L29/49 , H01L29/786 , H01L29/76
CPC分类号： H01L29/4908 , H01L27/124 , H01L27/1248 , H01L27/1255 , H01L27/1277 , H01L29/42384
摘要： A semiconductor device and a process for production thereof, said semiconductor device having a new electrode structure which has a low resistivity and withstands heat treatment at 400.degree. C. and above. Heat treatment at a high temperature (400-700.degree. C.) is possible because the wiring is made of Ta film or Ta-based film having high heat resistance. This heat treatment permits the gettering of metal element in crystalline silicon film. Since this heat treatment is lower than the temperature which the gate wiring (0.1-5 .mu.m wide) withstands and the gate wiring is protected with a protective film, the gate wiring retains its low resistance.
摘要翻译：一种半导体器件及其制造方法，所述半导体器件具有新的电极结构，该电极结构具有低电阻率并且可在400℃以上进行热处理。因为布线由具有高耐热性的Ta膜或Ta基膜制成，所以可以在高温（400-700℃）下进行热处理。该热处理允许在晶体硅膜中吸收金属元素。由于该热处理低于栅极布线（0.1-5μm宽）耐受并且栅极布线被保护膜保护的温度，所以栅极布线保持其低电阻。

97. 发明授权

US08581309B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08581309B2
公开(公告)日：2013-11-12
申请号：US13277489
申请日：2011-10-20
申请人： Shunpei Yamazaki , Atsuo Isobe , Hiromichi Godo , Yutaka Okazaki
发明人： Shunpei Yamazaki , Atsuo Isobe , Hiromichi Godo , Yutaka Okazaki
IPC分类号： H01L27/092
CPC分类号： H01L27/1266 , H01L21/823807 , H01L21/823871 , H01L23/433 , H01L23/481 , H01L23/552 , H01L27/0688 , H01L27/1214 , H01L27/1229 , H01L29/7843 , H01L2224/16 , H01L2224/73253 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12044 , H01L2924/16152 , H01L2924/16195
摘要： An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel field-effect transistors and p-channel field-effect transistors are stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. By controlling a distortion caused to a semiconductor layer due to an insulating film having a stress, a plane orientation of the semiconductor layer, and a crystal axis in a channel length direction, difference in mobility between the n-channel field-effect transistor and the p-channel field-effect transistor can be reduced, whereby current driving capabilities and response speeds of the n-channel field-effect transistor and the p-channel field-effect can be comparable.
摘要翻译：目的是在具有SOI结构的半导体器件中实现高性能和低功耗。此外，另一个目的是提供一种具有更高集成度的高性能半导体元件的半导体器件。半导体器件使得多个n沟道场效应晶体管和p沟道场效应晶体管层叠在其间具有绝缘表面的衬底之间的层间绝缘层。通过控制由于具有应力的绝缘膜，半导体层的平面取向和沟道长度方向的晶轴引起的半导体层的失真，n沟道场效应晶体管和可以减小p沟道场效应晶体管，由此n沟道场效应晶体管的电流驱动能力和响应速度与p沟道场效应相当。

98. 发明授权

US08044464B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08044464B2
公开(公告)日：2011-10-25
申请号：US12209739
申请日：2008-09-12
申请人： Shunpei Yamazaki , Atsuo Isobe , Hiromichi Godo , Yutaka Okazaki
发明人： Shunpei Yamazaki , Atsuo Isobe , Hiromichi Godo , Yutaka Okazaki
IPC分类号： H01L27/01
CPC分类号： H01L27/1266 , H01L21/823807 , H01L21/823871 , H01L23/433 , H01L23/481 , H01L23/552 , H01L27/0688 , H01L27/1214 , H01L27/1229 , H01L29/7843 , H01L2224/16 , H01L2224/73253 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12044 , H01L2924/16152 , H01L2924/16195
摘要： An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel field-effect transistors and p-channel field-effect transistors are stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. By controlling a distortion caused to a semiconductor layer due to an insulating film having a stress, a plane orientation of the semiconductor layer, and a crystal axis in a channel length direction, difference in mobility between the n-channel field-effect transistor and the p-channel field-effect transistor can be reduced, whereby current driving capabilities and response speeds of the n-channel field-effect transistor and the p-channel field-effect can be comparable.
摘要翻译：目的是在具有SOI结构的半导体器件中实现高性能和低功耗。此外，另一个目的是提供一种具有更高集成度的高性能半导体元件的半导体器件。半导体器件使得多个n沟道场效应晶体管和p沟道场效应晶体管层叠在其间具有绝缘表面的衬底之间的层间绝缘层。通过控制由于具有应力的绝缘膜，半导体层的平面取向和沟道长度方向的晶轴引起的半导体层的失真，n沟道场效应晶体管与可以减小p沟道场效应晶体管，由此n沟道场效应晶体管的电流驱动能力和响应速度与p沟道场效应相当。

99. 发明授权

US07982250B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07982250B2
公开(公告)日：2011-07-19
申请号：US12209696
申请日：2008-09-12
申请人： Shunpei Yamazaki , Atsuo Isobe , Hiromichi Godo , Yutaka Okazaki
发明人： Shunpei Yamazaki , Atsuo Isobe , Hiromichi Godo , Yutaka Okazaki
IPC分类号： H01L27/12
CPC分类号： H01L21/8221 , H01L27/0688 , H01L2224/16225 , H01L2224/16227 , H01L2224/32245 , H01L2924/00011 , H01L2924/00014 , H01L2224/29099 , H01L2224/13099 , H01L2224/80001
摘要： A semiconductor device is demonstrated in which a plurality of field-effect transistors is stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. Each of the plurality of filed-effect transistors has a semiconductor layer which is prepared by a process including separation of the semiconductor layer from a semiconductor substrate followed by bonding thereof over the substrate. Each of the plurality of field-effect transistors is covered with an insulating film which provides distortion of the semiconductor layer. Furthermore, the crystal axis of the semiconductor layer, which is parallel to the crystal plane thereof, is set to a channel length direction of the semiconductor layer, which enables production of the semiconductor device with high performance and low power consumption having an SOI structure.
摘要翻译：示出了一种半导体器件，其中在具有绝缘表面的衬底上层叠多个场效应晶体管，层间绝缘层介于其间。多个场效应晶体管中的每一个具有半导体层，该半导体层通过包括将半导体层与半导体衬底分离并随后在衬底上结合的工艺制备。多个场效应晶体管中的每一个被覆盖有提供半导体层失真的绝缘膜。此外，将半导体层的与其晶面平行的晶轴设定为半导体层的沟道长度方向，能够制造具有SOI结构的高性能，低功耗的半导体器件。

100. 发明授权

US07692194B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07692194B2
公开(公告)日：2010-04-06
申请号：US12015362
申请日：2008-01-16
申请人： Shunpei Yamazaki , Atsuo Isobe , Hiromichi Godo
发明人： Shunpei Yamazaki , Atsuo Isobe , Hiromichi Godo
IPC分类号： H01L29/04 , H01L31/036 , H01L31/0376 , H01L31/20
CPC分类号： H01L29/78621 , H01L29/42384 , H01L29/4908 , H01L29/66757 , H01L29/78618 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a novel structure by which the operating characteristics and reliability are improved and a manufacturing method thereof. An island-shaped semiconductor layer provided over a substrate, including a channel formation region provided between a pair of impurity regions; a first insulating layer provided so as to be in contact with the side surface of the semiconductor layer; a gate electrode provided over the channel formation region so as to get across the semiconductor layer; and a second insulating layer provided between the channel formation region and the gate electrode are included. The semiconductor layer is locally thinned, the channel formation region is provided in the thinned region, and the second insulating layer covers the first insulating layer provided on the side surface of the semiconductor layer at least in the region which overlaps with the gate electrode.
摘要翻译：具有改善其操作特性和可靠性的新颖结构的半导体器件及其制造方法。一种岛状半导体层，设置在衬底上，包括设置在一对杂质区之间的沟道形成区; 设置成与半导体层的侧表面接触的第一绝缘层; 栅电极，设置在所述沟道形成区上方以穿过所述半导体层; 并且包括设置在沟道形成区域和栅电极之间的第二绝缘层。半导体层被局部变薄，沟道形成区域设置在减薄区域中，并且第二绝缘层至少在与栅电极重叠的区域中覆盖设置在半导体层的侧表面上的第一绝缘层。

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