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91. 发明授权

US08609505B2 Method of forming MIM capacitor structure in FEOL 有权
标题翻译：在FEOL中形成MIM电容器结构的方法
公开(公告)号：US08609505B2
公开(公告)日：2013-12-17
申请号：US13359032
申请日：2012-01-26
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Robert M. Rassel , Anthony K. Stamper
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L27/06 , H01L27/07 , H01L21/20
CPC分类号： H01L27/0629 , H01L28/60
摘要： A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor plate; a capacitor dielectric layer formed over a second portion of the upper surface of the first capacitor plate and extending laterally beyond the spacer to contact the semiconductor substrate; a contact in an interlayer dielectric (ILD), the contact contacting the silicide layer and a first metal layer over the ILD; and a second capacitor plate over the capacitor dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed by the first capacitor plate, the capacitor dielectric layer and the second capacitor plate and a metal-insulator-semiconductor (MIS) capacitor is formed by the second capacitor plate, the capacitor dielectric layer and the semiconductor substrate.
摘要翻译：电容器结构包括半导体衬底; 位于所述半导体衬底上的第一电容器板，所述第一电容器板包括具有周围间隔物的多晶硅结构; 硅化物层，形成在所述第一电容器板的上表面的第一部分中; 电容器电介质层，形成在第一电容器板的上表面的第二部分上并且横向延伸超过间隔物以接触半导体衬底; 在层间电介质（ILD）中的接触，接触硅化物层的接触和ILD上的第一金属层; 以及在所述电容器电介质层上的第二电容器板，其中由所述第一电容器板，所述电容器介电层和所述第二电容器板以及金属 - 绝缘体 - 半导体（MIS）电容器形成金属 - 绝缘体 - 金属（MIM）电容器由第二电容器板，电容器电介质层和半导体衬底形成。

92. 发明授权

US08378450B2 Interdigitated vertical parallel capacitor 有权
标题翻译：交叉垂直并联电容器
公开(公告)号：US08378450B2
公开(公告)日：2013-02-19
申请号：US12548484
申请日：2009-08-27
申请人： Roger A. Booth, Jr. , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He
发明人： Roger A. Booth, Jr. , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/90 , H01L23/5223 , H01L28/86 , H01L2924/0002 , H01L2924/00
摘要： An interdigitated structure may include at least one first metal line, at least one second metal line parallel to the at least one first metal line and separated from the at least one first metal line, and a third metal line contacting ends of the at least one first metal line and separated from the at least one second metal line. The at least one first metal line does not vertically contact any metal via and at least one second metal line may vertically contact at least one metal via. Multiple layers of interdigitated structure may be vertically stacked. Alternately, an interdigitated structure may include a plurality of first metal lines and a plurality of second metal lines, each metal line not vertically contacting any metal via. Multiple instances of interdigitated structure may be laterally replicated and adjoined, with or without rotation, and/or vertically stacked to form a capacitor.
摘要翻译：叉指结构可以包括至少一个第一金属线，平行于至少一个第一金属线并与至少一个第一金属线分离的至少一个第二金属线，以及接触至少一个第一金属线的端部的第三金属线第一金属线并且与所述至少一个第二金属线分离。所述至少一个第一金属线不垂直接触任何金属通孔，并且至少一个第二金属线可垂直接触至少一个金属通孔。多层交错结构可以垂直堆叠。替代地，叉指结构可以包括多个第一金属线和多个第二金属线，每个金属线不垂直地接触任何金属通孔。交错结构的多个实例可以横向复制和邻接，具有或不具有旋转和/或垂直堆叠以形成电容器。

93. 发明授权

US08236663B2 Dual-damascene process to fabricate thick wire structure 有权
标题翻译：双镶嵌工艺制造粗线结构
公开(公告)号：US08236663B2
公开(公告)日：2012-08-07
申请号：US12564482
申请日：2009-09-22
申请人： Douglas D. Coolbaugh , Keith E. Downes , Peter J Lindgren , Anthony K. Stamper
发明人： Douglas D. Coolbaugh , Keith E. Downes , Peter J Lindgren , Anthony K. Stamper
IPC分类号： H01L21/20
CPC分类号： H01L23/481 , H01L21/76808 , H01L21/76813 , H01L21/76832 , H01L23/5223 , H01L28/60 , H01L2221/1036 , H01L2924/0002 , H01L2924/00
摘要： A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.
摘要翻译：一种方法和半导体器件。在该方法中，至少一个部分通孔被蚀刻成堆叠结构，围绕至少一个部分通孔形成边界。该方法还包括使用选择性蚀刻执行厚布线，同时通过蚀刻继续至少一个蚀刻停止层。

94. 发明授权

US08207568B2 Process for single and multiple level metal-insulator-metal integration with a single mask 有权
标题翻译：单层和多层金属绝缘体金属与单一掩模集成的工艺
公开(公告)号：US08207568B2
公开(公告)日：2012-06-26
申请号：US11162661
申请日：2005-09-19
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Keith E. Downes , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Keith E. Downes , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L29/92
CPC分类号： H01L21/32139 , H01L21/32136 , H01L28/75
摘要： Method of fabricating a MIM capacitor and MIM capacitor. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.
摘要翻译：制造MIM电容器和MIM电容器的方法。该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。上板被切下，使得上板的边缘位于掩模下方。使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。

95. 发明申请

US20120122293A1 METHOD OF FORMING MIM CAPACITOR STRUCTURE IN FEOL 有权
标题翻译：在FEOL中形成MIM电容结构的方法
公开(公告)号：US20120122293A1
公开(公告)日：2012-05-17
申请号：US13359032
申请日：2012-01-26
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Robert M. Rassel , Anthony K. Stamper
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L21/02
CPC分类号： H01L27/0629 , H01L28/60
摘要： A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor plate; a capacitor dielectric layer formed over a second portion of the upper surface of the first capacitor plate and extending laterally beyond the spacer to contact the semiconductor substrate; a contact in an interlayer dielectric (ILD), the contact contacting the silicide layer and a first metal layer over the ILD; and a second capacitor plate over the capacitor dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed by the first capacitor plate, the capacitor dielectric layer and the second capacitor plate and a metal-insulator-semiconductor (MIS) capacitor is formed by the second capacitor plate, the capacitor dielectric layer and the semiconductor substrate.
摘要翻译：电容器结构包括半导体衬底; 位于所述半导体衬底上的第一电容器板，所述第一电容器板包括具有周围间隔物的多晶硅结构; 硅化物层，形成在所述第一电容器板的上表面的第一部分中; 电容器电介质层，形成在第一电容器板的上表面的第二部分上并且横向延伸超过间隔物以接触半导体衬底; 在层间电介质（ILD）中的接触，接触硅化物层的接触和ILD上的第一金属层; 以及在所述电容器电介质层上的第二电容器板，其中由所述第一电容器板，所述电容器介电层和所述第二电容器板以及金属 - 绝缘体 - 半导体（MIS）电容器形成金属 - 绝缘体 - 金属（MIM）电容器由第二电容器板，电容器电介质层和半导体衬底形成。

96. 发明授权

US07919830B2 Method and structure for ballast resistor 有权
标题翻译：镇流电阻的方法和结构
公开(公告)号：US07919830B2
公开(公告)日：2011-04-05
申请号：US12062262
申请日：2008-04-03
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Kimball M. Watson
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Kimball M. Watson
IPC分类号： H01L21/8222
CPC分类号： H01L29/41708 , H01L27/0629 , H01L27/0658 , H01L29/66272 , H01L29/7322 , H01L29/78
摘要： A method for fabricating a low-value resistor such as a ballast resistor for bipolar junction transistors. The resistor may be fabricated using layers of appropriate sheet resistance so as to achieve low resistance values in a compact layout. The method may rely on layers already provided by a conventional CMOS process flow, such as contact plugs and fully silicided (FUSI) metal gates.
摘要翻译：一种用于制造低电阻电阻器的方法，例如用于双极结型晶体管的镇流电阻器。可以使用适当的薄层电阻的层来制造电阻器，以便在紧凑的布局中实现低电阻值。该方法可以依赖于传统CMOS工艺流程已经提供的层，例如接触插塞和完全硅化（FUSI）金属栅极。

97. 发明授权

US07768055B2 Passive components in the back end of integrated circuits 失效
标题翻译：集成电路后端的被动元件
公开(公告)号：US07768055B2
公开(公告)日：2010-08-03
申请号：US11164634
申请日：2005-11-30
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Jeffrey B. Johnson , Jonghae Kim , Jean-Oliver Plouchart , Anthony K. Stamper
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Jeffrey B. Johnson , Jonghae Kim , Jean-Oliver Plouchart , Anthony K. Stamper
IPC分类号： H01L29/94
CPC分类号： H01L23/5228 , H01L23/5227 , H01L28/87 , H01L2924/0002 , H01L2924/00
摘要： Passive components are formed in the back end by using the same deposition process and materials as in the rest of the back end. Resistors are formed by connecting in series individual structures on the nth, (n+1)th, etc levels of the back end. Capacitors are formed by constructing a set of vertical capacitor plates from a plurality of levels in the back end, the plates being formed by connecting electrodes on two or more levels of the back end by vertical connection members.
摘要翻译：通过使用与后端的其余部分相同的沉积工艺和材料在后端形成被动部件。电阻器通过连接在后端的第n（n + 1）等级上的串联单独结构而形成。电容器通过从后端的多个层构造一组垂直电容器板而形成，该板通过垂直连接构件在后端的两层或更多层上连接电极而形成。

98. 发明授权

US07728372B2 Method and structure for creation of a metal insulator metal capacitor 有权
标题翻译：制造金属绝缘子金属电容器的方法和结构
公开(公告)号：US07728372B2
公开(公告)日：2010-06-01
申请号：US11382544
申请日：2006-05-10
申请人： Ebenezer E. Eshun , Ronald J. Bolam , Douglas D. Coolbaugh , Keith E. Downes , Natalie B. Feilchenfeld , Zhong-Xiang He
发明人： Ebenezer E. Eshun , Ronald J. Bolam , Douglas D. Coolbaugh , Keith E. Downes , Natalie B. Feilchenfeld , Zhong-Xiang He
IPC分类号： H01L29/92
CPC分类号： H01L28/60
摘要： The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.
摘要翻译：本发明涉及一种改进的电容器，其减少边缘缺陷并防止产量失效。本发明的第一实施例包括与导电层与绝缘体的界面相邻的保护层，而本发明的第二实施例包括位于导电层上的绝缘体上的保护层。

99. 发明授权

US07700453B2 Method for forming hyper-abrupt junction varactors 失效
标题翻译：形成超突变连接变容二极管的方法
公开(公告)号：US07700453B2
公开(公告)日：2010-04-20
申请号：US11697886
申请日：2007-04-09
申请人： Douglas D. Coolbaugh , Stephen S. Furkay , Jeffrey B. Johnson , Robert M. Rassel , David C. Sheridan
发明人： Douglas D. Coolbaugh , Stephen S. Furkay , Jeffrey B. Johnson , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L21/20 , H01L21/8234 , H01L21/425
CPC分类号： H01L29/93 , H01L29/94
摘要： Method of fabricating a varactor that includes providing a semiconductor substrate, doping a lower region of the semiconductor substrate with a first dopant at a first energy level, doping a middle region of the semiconductor substrate with a second dopant at a second energy level lower than the first energy level, and doping an upper region of the semiconductor substrate with a third dopant at a third energy level lower than the second energy level.
摘要翻译：一种制造变容二极管的方法，包括提供半导体衬底，以第一能级掺杂第一掺杂剂的半导体衬底的下部区域，在第二能级下掺杂第二掺杂剂的第二掺杂剂的中间区域; 第一能级，并且以比第二能级低的第三能级用第三掺杂剂掺杂半导体衬底的上部区域。

100. 发明授权

US07670921B2 Structure and method for self aligned vertical plate capacitor 失效
标题翻译：自对准立板电容器的结构和方法
公开(公告)号：US07670921B2
公开(公告)日：2010-03-02
申请号：US11616955
申请日：2006-12-28
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Richard P. Volant
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Timothy J. Dalton , Ebenezer E. Eshun , Jeffrey P. Gambino , Anthony K. Stamper , Richard P. Volant
IPC分类号： H01L21/4763
CPC分类号： H01G4/33 , H01G4/005 , H01L23/5223 , H01L28/90 , H01L2924/0002 , Y10T29/417 , H01L2924/00
摘要： A method of forming a metal-insulator-metal (MIM) capacitor includes forming a first planar dielectric layer with a first metallization layer therein; forming a first passivation layer on top thereof; forming a planar conductive layer above the first passivation layer; patterning and selectively removing the conductive layer up to the first passivation layer in designated areas to form a set of conductive features; patterning and conformally coating the set of conductive features and the exposed first passivation layer with a high strength dielectric coating; disposing a second dielectric layer above the first passivation layer and enclosing the set of conductive features; patterning and selectively removing portions of the second substrate to form channels and trenches; performing a dual-Damascene process to form a second metallization layer in the trenches and channels and to form an upper conductive surface above the high strength dielectric coating.
摘要翻译：形成金属 - 绝缘体 - 金属（MIM）电容器的方法包括在其中形成第一平面介质层和第一金属化层; 在其顶部形成第一钝化层; 在所述第一钝化层上形成平面导电层; 在指定区域中图案化和选择性地去除导电层直到第一钝化层以形成一组导电特征; 用高强度电介质涂层构图和保形地涂覆该组导电特征和暴露的第一钝化层; 在所述第一钝化层上设置第二电介质层并且包围所述一组导电特征; 图案化和选择性地去除第二衬底的部分以形成沟道和沟槽; 执行双镶嵌工艺以在沟槽和通道中形成第二金属化层，并在高强度电介质涂层上形成上导电表面。

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