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91. 发明授权

US07218604B2 Orthogonal frequency division multiplexing system with differing control parameters corresponding to different data points in a single symbol 有权
标题翻译：具有不同控制参数的正交频分复用系统对应于单个符号中的不同数据点
公开(公告)号：US07218604B2
公开(公告)日：2007-05-15
申请号：US10060502
申请日：2002-01-30
申请人： Srinath Hosur , Dennis Rauschmayer
发明人： Srinath Hosur , Dennis Rauschmayer
IPC分类号： H04J11/00
CPC分类号： H04L27/2602
摘要： A wireless transmitter (TX1). The transmitter comprises circuitry for providing a plurality of control (CONTROL) bits and circuitry for providing a plurality of user (USER) bits. The transmitter also comprises circuitry for modulating (16) the plurality of control bits and the plurality of user bits into a stream of complex symbols and circuitry (18) for converting the stream of complex symbols into a parallel plurality of complex symbol streams. The transmitter also comprises circuitry (20) for performing an inverse fast Fourier transform on the parallel plurality of complex symbol streams to form a parallel plurality of OFDM symbols and circuitry (22) for converting the parallel plurality of OFDM symbols into a serial stream of OFDM symbols. Each OFDM symbol in the serial stream of OFDM symbols comprises a plurality of data points, and selected (SF2.x) OFDM symbols in the serial stream of OFDM symbols carry modulation information (AMOD). The modulation information in one or more of the selected OFDM symbols comprises a plurality of modulation groups, and the plurality of modulation groups comprises a number of modulation parameters that describe modulation of a corresponding set of data points in a subsequent OFDM symbol in the serial stream of OFDM symbols.
摘要翻译：无线发射机（TX <1> ）。发射机包括用于提供多个控制（CONTROL）比特和用于提供多个用户（USER）比特）的电路的电路。所述发射机还包括用于将所述多个控制比特和所述多个用户比特调制（16）为复数符号流和电路（18）的电路，用于将复符号流转换为并行多个复符号流。发射机还包括用于对并行多个复符号流执行快速傅立叶逆变换的电路（20），以形成并行多个OFDM符号和电路（22），用于将并行多个OFDM符号转换成OFDM的串行流符号。 OFDM符号的串行流中的每个OFDM符号包括多个数据点，并且在OFDM符号的串行流中选择的（SF×2.×N）个OFDM符号携带调制信息（AMOD）。所选择的OFDM符号中的一个或多个中的调制信息包括多个调制组，并且所述多个调制组包括多个调制参数，所述调制参数描述在串行流中随后的OFDM符号中对应的一组数据点的调制的OFDM符号。

92. 发明申请

US20060222099A1 Channel length estimation and accurate FFT window placement for high-mobility OFDM receivers in single frequency networks 有权
标题翻译：信道长度估计和单频网络中高移动性OFDM接收机的精确FFT窗口布局
公开(公告)号：US20060222099A1
公开(公告)日：2006-10-05
申请号：US11389354
申请日：2006-03-23
申请人： Badri Varadarajan , Anand Dabak , Charles Sestok , Srinath Hosur
发明人： Badri Varadarajan , Anand Dabak , Charles Sestok , Srinath Hosur
IPC分类号： H04L27/06 , H04K1/10
CPC分类号： H04L25/0216 , H04L27/2662 , H04L2025/03414
摘要： A method of estimating a channel length (304) in a wireless receiver is disclosed. The receiver receives a signal (122) from a remote transmitter. The receiver selects a plurality (K) of different candidate channel lengths and determines a respective criterion value (402) of the signal for each of the plurality of different candidate channel lengths. The receiver selects a channel length (410) from the plurality of different candidate channel lengths in response to the respective criterion value (404).
摘要翻译：公开了一种在无线接收机中估计信道长度（304）的方法。接收机从远程发射机接收信号（122）。接收机选择不同候选信道长度的多个（K），并且为多个不同候选信道长度中的每一个确定信号的相应标准值（402）。接收机响应于各自的标准值（404）从多个不同候选信道长度中选择一个信道长度（410）。

93. 发明授权

US07103085B1 Wireless communications system with secondary synchronization code based on values in primary synchronization code 有权
标题翻译：基于主同步码中的值的无线通信系统具有辅同步码
公开(公告)号：US07103085B1
公开(公告)日：2006-09-05
申请号：US09595561
申请日：2000-06-16
申请人： Anand G. Dabak , Sundararajan Sriram , Srinath Hosur
发明人： Anand G. Dabak , Sundararajan Sriram , Srinath Hosur
IPC分类号： H04B1/38
CPC分类号： H04B1/7083 , H04B1/70735 , H04J13/00 , H04J13/12
摘要： A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a secondary synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences. The third sequence comprises a subset of bits from the first sequence.
摘要翻译：无线通信系统。该系统包括发射机电路（BST1），发射机电路包括用于传输多个帧（FR）的编码器电路（50）。多个帧中的每一个包括主同步码（PCS）和辅同步码（SSC）。编码器电路包括用于响应于第一序列（32）提供主同步码的电路（50 1）。编码器电路还包括用于响应于第二序列（54）和第三序列（56）提供辅助同步码的电路（50）。第二序列从多个序列中选择。多个序列中的每一个相对于多个序列中的所有其他序列是正交的。第三序列包括来自第一序列的比特的子集。

94. 发明授权

US06999981B2 Circuit for computing the absolute value of complex numbers 有权
标题翻译：用于计算复数绝对值的电路
公开(公告)号：US06999981B2
公开(公告)日：2006-02-14
申请号：US10057137
申请日：2002-01-25
申请人： Manish Goel , Srinath Hosur , Michael O. Polley
发明人： Manish Goel , Srinath Hosur , Michael O. Polley
IPC分类号： G06F7/00 , G06F7/38
CPC分类号： G06F7/552 , G06F7/4806
摘要： An apparatus (100) for computing the absolute value of a complex number includes separate squaring units (110, 115) for the real and imaginary parts. A square root unit (130) extracts the square root of the sum (120) of these squares, which is absolute value of the complex number. Each squaring unit includes one unsigned multipliers for respective least significant and two signed multipliers for respective most significant bits and a cross term. The products are aligned by shifting and summed. The square root unit employs identical processing elements, each considering two bits of the input and forming one root bit and a remainder. Each processing element compares two intermediate test variables, and selects a “1” or “0” for the root bit and the next remainder based upon this comparison. A chain of processing elements enables computation of the root to the desired precision. Alternatively, the same processing elements may be used in a recirculating manner.
摘要翻译：用于计算复数的绝对值的装置（100）包括用于实部和虚部的分立的平方单元（110,115）。平方根单元（130）提取这些正方形的和（120）的平方根，其是复数的绝对值。每个平方单元包括用于相应最低有效位的一个无符号乘法器和用于相应最高有效位的两个有符号乘法器和交叉项。产品通过移位和相加进行对齐。平方根单元采用相同的处理元件，每个元件考虑输入的两个位，并形成一个根位和余数。每个处理元件比较两个中间测试变量，并根据该比较为根位选择“1”或“0”。一系列处理元件能够将根计算到所需的精度。或者，可以以循环方式使用相同的处理元件。

95. 发明授权

US06977910B1 Power control with space time transmit diversity 有权
标题翻译：功率控制与时空发射分集
公开(公告)号：US06977910B1
公开(公告)日：2005-12-20
申请号：US09224401
申请日：1998-12-31
申请人： Srinath Hosur , Anand G. Dabak
发明人： Srinath Hosur , Anand G. Dabak
IPC分类号： H04B1/00 , H04B1/02 , H04B1/707 , H04B7/005 , H04B7/185 , H04B7/216
CPC分类号： H04B7/0669 , H04B1/712 , H04B2201/70707 , H04W52/08 , H04W52/241 , H04W52/245 , H04W52/42
摘要： A circuit is designed with a measurement circuit (432). The measurement circuit is coupled to receive a first input signal (903) from a first antenna (128) of a transmitter and coupled to receive a second input signal (913) from a second antenna (130) of the transmitter. Each of the first and second signals is transmitted at a first time. The measurement circuit produces an output signal corresponding to a magnitude of the first and second signals. A control circuit (430) is coupled to receive the output signal and a reference signal. The control circuit is arranged to produce a control signal at a second time in response to a comparison of the output signal and the reference signal.
摘要翻译：电路设计有测量电路（432）。测量电路被耦合以从发射机的第一天线（128）接收第一输入信号（903），并被耦合以从发射机的第二天线（130）接收第二输入信号（913）。第一和第二信号中的每一个在第一时间被发送。测量电路产生对应于第一和第二信号的幅度的输出信号。控制电路（430）被耦合以接收输出信号和参考信号。控制电路被布置成响应于输出信号和参考信号的比较而在第二时间产生控制信号。

96. 发明申请

US20050113041A1 Frequency-domain subchannel transmit antenna selection and power pouring for multi-antenna transmission 有权
标题翻译：用于多天线传输的频域子信道发射天线选择和电力倾倒
公开(公告)号：US20050113041A1
公开(公告)日：2005-05-26
申请号：US10723215
申请日：2003-11-26
申请人： Michael Polley , Donald Shaver , Srinath Hosur , Eko Onggosanusi , Muhammad Ikram , Anand Dabak
发明人： Michael Polley , Donald Shaver , Srinath Hosur , Eko Onggosanusi , Muhammad Ikram , Anand Dabak
IPC分类号： H04B7/005 , H04B1/02
CPC分类号： H04W52/42
摘要： A system comprises a wireless device that communicates across a spectrum having a plurality of sub-channels. The wireless device comprises a plurality of antennas through which the wireless device communicates with another wireless device, wherein each antenna communicates with the other wireless device via an associated communication pathway. The wireless device further comprises sub-channel power analysis logic coupled to the antennas and adapted to determine which communication pathway has the highest communication quality on a sub-channel by sub-channel basis. The wireless device still further comprises diversity selection logic coupled to the sub-channel power analysis logic and adapted to determine a weighting vector for an associated antenna based on the communication quality, wherein the weighting vector specifies a relative transmission power for each sub-channel for the associated antenna.
摘要翻译：一种系统包括在具有多个子信道的频谱上进行通信的无线设备。无线设备包括多个天线，无线设备通过多个天线与另一无线设备通信，其中每个天线经由相关联的通信路径与另一无线设备进行通信。无线设备还包括耦合到天线的子信道功率分析逻辑，并且适于通过子信道来确定子信道上哪个通信路径具有最高通信质量。无线设备还包括耦合到子信道功率分析逻辑的分集选择逻辑，并且适于基于通信质量来确定相关天线的加权矢量，其中加权向量规定每个子信道的相对发射功率，用于相关天线。

97. 发明申请

US20050044472A1 Wireless access modem having downstream channel resynchronization method 有权
标题翻译：具有下行信道重新同步方式的无线接入调制解调器
公开(公告)号：US20050044472A1
公开(公告)日：2005-02-24
申请号：US10643119
申请日：2003-08-18
申请人： Xiaolin Lu , Srinath Hosur , Manish Goel , Michael Polley
发明人： Xiaolin Lu , Srinath Hosur , Manish Goel , Michael Polley
IPC分类号： H03M13/00 , H04B1/38 , H04L7/04 , H04L7/10
CPC分类号： H04W56/009 , H04L7/048 , H04L7/10 , H04W24/00 , H04W74/00
摘要： A resynchronization method for use in a data communication system having a first device configured to transmit data at a symbol rate to a second device. The second device includes a Reed Solomon (RS) decoder having a RS lock indicator and a Moving Picture Experts Group (MPEG) Protocol Interface (MPI) having a MPI lock indicator, wherein the RS and the MPI lock indicators are monitored. Four different states, defined by the values of the RS and MPI lock indicators, determine whether the data communication system will wait for the RS decoder and the MPI hardware block to resynchronize, whether an intermediate-subset of the channel acquisition algorithm is performed or whether the entire channel acquisition algorithm is performed. The method for resynchronization described herein recovers synchronization within a predetermined time without the layers above the physical link layer having knowledge.
摘要翻译：一种用于具有第一设备的数据通信系统中的再同步方法，该第一设备被配置为以符号速率向第二设备发送数据。第二装置包括具有RS锁定指示器的里德所罗门（RS）解码器和具有MPI锁定指示器的运动图像专家组（MPEG）协议接口（MPI），其中监测RS和MPI锁定指示符。由RS和MPI锁指示符的值定义的四种不同状态确定数据通信系统是否将等待RS解码器和MPI硬件块重新同步，无论是执行信道获取算法的中间子集还是执行执行整个信道获取算法。本文所述的用于重新同步的方法在预定时间内恢复同步，而不具有物理链路层之上的层具有知识。

98. 发明申请

US20050018646A1 Multistage PN code acquisition circuit and method 有权
标题翻译：多级PN码采集电路及方法
公开(公告)号：US20050018646A1
公开(公告)日：2005-01-27
申请号：US10918839
申请日：2004-08-13
申请人： Sundararajan Sriram , Srinath Hosur
发明人： Sundararajan Sriram , Srinath Hosur
IPC分类号： H04B1/707 , H04K1/00
CPC分类号： H04B1/70752 , H04B1/70735 , H04B1/7077 , H04B1/7093 , H04B2201/70702 , H04B2201/70707
摘要： A circuit for detecting a serial signal comprises a first circuit (400) coupled to receive the serial signal (200) during a predetermined plurality of time periods of substantially equal duration. The first circuit is coupled to receive a first code (414). The first circuit is arranged to compare a part of the serial signal corresponding to each time period of the plurality of time periods to the first code, thereby producing a match signal. The first circuit accumulates the match signal from each of the each time period of the plurality of time periods.
摘要翻译：用于检测串行信号的电路包括第一电路（400），该第一电路被耦合以在基本相等的持续时间的预定多个时间段内接收串行信号（200）。第一电路被耦合以接收第一代码（414）。第一电路被布置为将与多个时间段的每个时间段相对应的串行信号的一部分与第一代码进行比较，从而产生匹配信号。第一电路从多个时间段的每个时间段的每一个累加匹配信号。

99. 发明授权

US08923362B2 Wireless communications system with secondary synchronization code based on values in primary synchronization code 有权
公开(公告)号：US08923362B2
公开(公告)日：2014-12-30
申请号：US13403201
申请日：2012-02-23
申请人： Anand G. Dabak , Sundararajan Sriram , Srinath Hosur
发明人： Anand G. Dabak , Sundararajan Sriram , Srinath Hosur
IPC分类号： H04B1/69 , H04B1/707 , H04B1/713 , H04B1/7083 , H04B1/7073 , H04J13/00 , H04J13/12
CPC分类号： H04B1/7083 , H04B1/70735 , H04J13/00 , H04J13/12
摘要： A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a second synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences. The third sequence is a subset of bits from the first sequence.

100. 发明授权

US08681834B2 Wireless communications system with secondary synchronization code based on values in primary synchronization code 有权
标题翻译：基于主同步码中的值的无线通信系统具有辅同步码
公开(公告)号：US08681834B2
公开(公告)日：2014-03-25
申请号：US13403236
申请日：2012-02-23
申请人： Anand G. Dabak , Sundararajan Sriram , Srinath Hosur
发明人： Anand G. Dabak , Sundararajan Sriram , Srinath Hosur
IPC分类号： H04B1/69 , H04B1/707 , H04B1/713
CPC分类号： H04B1/7083 , H04B1/70735 , H04J13/00 , H04J13/12
摘要： A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a second synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences. The third sequence is a subset of bits from the first sequence.
摘要翻译：无线通信系统。该系统包括发射机电路（BST1），该发射机电路包括用于传输多个帧（FR）的编码器电路（50）。多个帧中的每一个包括主同步码（PCS）和第二同步码（SSC）。编码器电路包括用于响应于第一序列（32）提供主同步码的电路（501）。编码器电路还包括用于响应于第二序列（54）和第三序列（56）提供辅助同步码的电路（502）。第二序列从多个序列中选择。多个序列中的每一个相对于所有其他序列是正交的。第三个序列是来自第一个序列的比特的子集。

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