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91. 发明授权

US08541293B2 Method of controlled lateral etching 有权
标题翻译：受控横向蚀刻方法
公开(公告)号：US08541293B2
公开(公告)日：2013-09-24
申请号：US13509604
申请日：2011-11-23
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/36 , H01L21/84 , H01L21/00 , H01L21/336
CPC分类号： H01L21/823431 , H01L21/31144 , H01L21/823821 , H01L21/84 , H01L21/845
摘要： A method of controlled lateral etching is disclosed. In one embodiment, the method may comprise: forming on a first material layer, which comprises a protruding structure, a second material layer; forming spacers on outer surfaces of the second material layer opposite to vertical surfaces of the protruding structure; forming a third material layer on surfaces of the second material layer and the spacers; forming on the third material layer a mask layer which extends in a direction lateral to a surface of the first material layer; and laterally etching portions of the respective layers arranged on the vertical surfaces of the protruding structure.
摘要翻译：公开了一种受控横向蚀刻的方法。在一个实施例中，该方法可以包括：在包括突出结构的第一材料层上形成第二材料层; 在所述第二材料层的与所述突出结构的垂直表面相对的外表面上形成间隔物; 在所述第二材料层和所述间隔物的表面上形成第三材料层; 在所述第三材料层上形成在所述第一材料层的表面的横向方向上延伸的掩模层; 并横向蚀刻布置在突出结构的垂直表面上的各个层的部分。

92. 发明授权

US08470662B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08470662B2
公开(公告)日：2013-06-25
申请号：US13063538
申请日：2010-06-28
申请人： Zhijiong Luo , Huilong Zhu , Haizhou Yin
发明人： Zhijiong Luo , Huilong Zhu , Haizhou Yin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823864 , H01L21/28176 , H01L29/4966 , H01L29/517 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： The present invention relates to a semiconductor device and a manufacturing method for making the same, wherein, according to the method, after the gate stack is formed, a buffer layer is formed on sidewalls of an PMOS gate stack, the buffer layer being formed of a porous low-k dielectric layer; and then, sidewall spacers and source/drain/halo regions, and source and drain regions are formed for the device; and finally, a high-temperature anneal is conducted in an oxygen environment such that the oxygen in the oxygen environment diffuse through the buffer layer into the high-k dielectric layer of the second gate stack. The present invention lowers threshold voltage of the PMOS device without affecting the threshold voltage of the NMOS device, avoids damages to the gate and substrate incurred by removing the PMOS sidewall spacer in a traditional process, and hereby effectively improves the overall performance of the device.
摘要翻译：半导体器件及其制造方法技术领域本发明涉及一种半导体器件及其制造方法，其中，根据该方法，在形成栅极叠层之后，在PMOS栅极叠层的侧壁上形成缓冲层，缓冲层由多孔低k电介质层; 然后为器件形成侧壁间隔物和源极/漏极/晕圈区域以及源极和漏极区域; 最后，在氧环境中进行高温退火，使得氧环境中的氧气通过缓冲层扩散到第二栅极叠层的高k电介质层。本发明降低了PMOS器件的阈值电压，而不影响NMOS器件的阈值电压，避免了在传统工艺中去除PMOS侧壁间隔物对栅极和衬底的损坏，从而有效地提高了器件的整体性能。

93. 发明授权

US08466500B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08466500B2
公开(公告)日：2013-06-18
申请号：US13063977
申请日：2011-02-24
申请人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L33/12
CPC分类号： H01L29/7848 , H01L29/0653 , H01L29/1083 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7849
摘要： The present invention discloses a semiconductor device and a method for manufacturing the same, and relates to the field of semiconductor manufacturing. According to the present invention, the semiconductor device comprises: a semiconductor substrate; a gate region located above the semiconductor substrate; S/D regions located at both sides of the gate region and made of a stress material; wherein a concentrated stress region is formed between the gate region and the semiconductor substrate, and the concentrated stress region comprises an upper SOI layer adjacent to the gate region above, and a lower stress release layer adjacent to the semiconductor substrate below. The present invention applies to the manufacturing of a MOSFET.
摘要翻译：本发明公开了一种半导体器件及其制造方法，涉及半导体制造领域。根据本发明，半导体器件包括：半导体衬底; 位于半导体衬底上方的栅极区域; S / D区域位于栅极区域的两侧并由应力材料制成; 其中在所述栅极区域和所述半导体衬底之间形成集中应力区域，并且所述集中应力区域包括与所述栅极区域相邻的上部SOI层以及与所述半导体衬底相邻的较低应力释放层。本发明适用于MOSFET的制造。

94. 发明授权

US08450775B2 Method to control source/drain stressor profiles for stress engineering 有权
标题翻译：控制应力工程源/排泄应力曲线的方法
公开(公告)号：US08450775B2
公开(公告)日：2013-05-28
申请号：US13229773
申请日：2011-09-12
申请人： Yung Fu Chong , Zhijiong Luo , Judson Robert Holt
发明人： Yung Fu Chong , Zhijiong Luo , Judson Robert Holt
IPC分类号： H01L21/02
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： An example embodiment of a strained channel transistor structure comprises the following: a strained channel region comprising a first semiconductor material with a first natural lattice constant; a gate dielectric layer overlying the strained channel region; a gate electrode overlying the gate dielectric layer; and a source region and drain region oppositely adjacent to the strained channel region, one or both of the source region and drain region are comprised of a stressor region comprised of a second semiconductor material with a second natural lattice constant different from the first natural lattice constant; the stressor region has a graded concentration of a dopant impurity and/or of a stress inducing molecule. Another example embodiment is a process to form the graded impurity or stress inducing molecule stressor embedded S/D region, whereby the location/profile of the S/D stressor is not defined by the recess depth/profile.
摘要翻译：应变通道晶体管结构的示例性实施例包括以下：包含具有第一自然晶格常数的第一半导体材料的应变通道区域; 覆盖在应变通道区上的栅介质层; 覆盖所述栅介质层的栅电极; 以及源极区域和漏极区域，其与所述应变通道区域相邻地邻近，所述源极区域和漏极区域中的一个或两个由包含第二半导体材料的应力区域构成，所述第二半导体材料具有不同于所述第一自然晶格常数的第二自然晶格常数 ; 应力区域具有掺杂剂杂质和/或应力诱导分子的分级浓度。另一个示例性实施例是形成渐变杂质或应力诱导分子应力嵌入S / D区域的过程，由此S / D应力器的位置/轮廓不由凹槽深度/轮廓限定。

95. 发明申请

US20130119484A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130119484A1
公开(公告)日：2013-05-16
申请号：US13063907
申请日：2011-02-27
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L29/51 , H01L29/40
CPC分类号： H01L29/518 , H01L29/401 , H01L29/4983 , H01L29/66477 , H01L29/78
摘要： The present invention provides a method of manufacturing a semiconductor device comprising: providing a semiconductor substrate, on which a high-k dielectric layer and a patterned gate are formed sequentially; nitridating portions of the high-k dielectric layer on the semiconductor substrate which are not covered by the gate; and forming spacers around the gate. Accordingly, the present invention further provides a semiconductor device. Portions of the high-k dielectric layer on the semiconductor substrate, which are not covered by the gate or the spacers positioned thereon, are nitridated, such that an oxygen diffusion barrier layer is formed on the surface of the high-k dielectric layer, thereby oxygen diffusion in the lateral direction into the high-k dielectric layer under the gate is prevented, and the operation performance of the semiconductor device is optimized.
摘要翻译：本发明提供一种制造半导体器件的方法，包括：提供半导体衬底，其上依次形成高k电介质层和图案化栅极; 半导体衬底上未被栅极覆盖的高k电介质层的氮化部分; 并在栅极周围形成间隔物。因此，本发明还提供一种半导体器件。半导体衬底上没有被栅极或位于其上的间隔物覆盖的高k电介质层的部分被氮化，使得在高k电介质层的表面上形成氧扩散阻挡层，从而防止在栅极下的高k电介质层的横向氧扩散，并优化半导体器件的操作性能。

96. 发明授权

US08440532B2 Structure and method for making metal semiconductor field effect transistor (MOSFET) with isolation last process 失效
标题翻译：制造具有隔离最后工艺的金属半导体场效应晶体管（MOSFET）的结构和方法
公开(公告)号：US08440532B2
公开(公告)日：2013-05-14
申请号：US12844478
申请日：2010-07-27
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L21/76224 , H01L21/76898 , H01L21/823481 , H01L27/1203
摘要： In one embodiment, a method of providing a semiconductor device is provided, in which instead of forming isolation regions before the formation of the semiconductor devices, the isolation regions are formed after the semiconductor devices. In one embodiment, the method includes forming a semiconductor device on a semiconductor substrate. A placeholder dielectric is formed on a portion of a first surface of the substrate adjacent to the semiconductor device. A trench is etched into the substrate from a second surface of the substrate that is opposite the first surface of the substrate, wherein the trench terminates on the placeholder dielectric. The trench is filled with a dielectric material.
摘要翻译：在一个实施例中，提供了提供半导体器件的方法，其中代替在形成半导体器件之前形成隔离区域，在半导体器件之后形成隔离区域。在一个实施例中，该方法包括在半导体衬底上形成半导体器件。在与半导体器件相邻的衬底的第一表面的一部分上形成占位电介质。沟槽从衬底的与衬底的第一表面相对的第二表面蚀刻到衬底中，其中沟槽终止在占位符电介质上。沟槽填充有电介质材料。

97. 发明授权

US08426282B2 Method for forming semiconductor substrate isolation 有权
标题翻译：形成半导体衬底隔离的方法
公开(公告)号：US08426282B2
公开(公告)日：2013-04-23
申请号：US13202606
申请日：2011-04-08
申请人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
发明人： Haizhou Yin , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L21/76243
摘要： The present invention provides a method for forming a semiconductor substrate isolation, comprising: providing a semiconductor substrate; forming a first oxide layer and a nitride layer sequentially on the semiconductor substrate; forming openings in the nitride layer and in the first oxide layer to expose parts of the semiconductor substrate; implanting oxygen ions into the semiconductor substrate from the openings; performing annealing to form a second oxide layer on at least top portions of the exposed parts of the semiconductor substrate; and removing the nitride layer and the first oxide layer. Compared to the conventional STI process, said method enables a more simply and easy process flow and is applicable to common semiconductor substrates and SOI substrates.
摘要翻译：本发明提供一种形成半导体衬底隔离的方法，包括：提供半导体衬底; 在半导体衬底上依次形成第一氧化物层和氮化物层; 在所述氮化物层和所述第一氧化物层中形成开口以暴露所述半导体衬底的部分; 从开口将氧离子注入半导体衬底; 进行退火以在半导体衬底的暴露部分的至少顶部上形成第二氧化物层; 以及去除氮化物层和第一氧化物层。与常规STI工艺相比，所述方法能够实现更简单和简单的工艺流程，并且可应用于常见的半导体衬底和SOI衬底。

98. 发明申请

US20130062699A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130062699A1
公开(公告)日：2013-03-14
申请号：US13576550
申请日：2011-11-25
申请人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/04 , H01L21/336
CPC分类号： H01L29/785 , H01L27/0924 , H01L29/66795
摘要： A semiconductor device and a method for manufacturing the same are disclosed. In one embodiment, the semiconductor device may comprise a semiconductor layer, a fin formed by patterning the semiconductor layer, and a gate stack crossing over the fin. The fin may comprise a doped block region at the bottom portion thereof. According to the embodiment, it is possible to effectively suppress current leakage at the bottom portion of the fin by the block region.
摘要翻译：公开了一种半导体器件及其制造方法。在一个实施例中，半导体器件可以包括半导体层，通过图案化半导体层形成的鳍和跨在翅片上的栅极堆叠。鳍可以在其底部包括掺杂块区域。根据本实施方式，能够通过块区域有效地抑制翅片底部的电流泄漏。

99. 发明申请

US20130056829A1 Semiconductor Structure and Method for Manufacturing the Same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20130056829A1
公开(公告)日：2013-03-07
申请号：US13504935
申请日：2011-11-30
申请人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
发明人： Huilong Zhu , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L27/092 , H01L21/02
CPC分类号： H01L27/124 , H01L21/743 , H01L27/1218 , H01L29/78
摘要： The present invention relates to a semiconductor structure and a method for manufacturing the same. A semiconductor structure comprises: a semiconductor substrate; a first insulating material layer, a first conductive material layer, a second insulating material layer, a second conductive material layer and an insulating buried layer formed in sequence on the semiconductor substrate; a semiconductor layer bonded on the insulating buried layer; transistors formed on the semiconductor layer, the channel regions of the transistors each being formed in the semiconductor layer and each having a back-gate formed from the second conductive material layer; a dielectric layer covering the semiconductor layer and the transistors; isolation structures for at least electrically isolating each transistor from its adjacent transistors, the top of the isolation structures being flush with or slightly higher than the upper surface of the semiconductor layer, and the bottom of the isolation structures being in the second insulating material layer; and a conductive contact running through the dielectric layer and extending down into the first conductive material layer.
摘要翻译：半导体结构及其制造方法技术领域本发明涉及半导体结构及其制造方法。半导体结构包括：半导体衬底; 在半导体衬底上依次形成第一绝缘材料层，第一导电材料层，第二绝缘材料层，第二导电材料层和绝缘掩埋层; 接合在绝缘掩埋层上的半导体层; 形成在半导体层上的晶体管，晶体管的沟道区各自形成在半导体层中，每一个具有由第二导电材料层形成的背栅; 覆盖半导体层和晶体管的电介质层; 用于至少将每个晶体管与其相邻晶体管电隔离的隔离结构，隔离结构的顶部与半导体层的上表面齐平或略高，隔离结构的底部位于第二绝缘材料层中; 以及导电接触件，其穿过介电层并向下延伸到第一导电材料层中。

100. 发明申请

US20130049117A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130049117A1
公开(公告)日：2013-02-28
申请号：US13510807
申请日：2011-11-18
申请人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
发明人： Huilong Zhu , Qingqing Liang , Zhijiong Luo , Haizhou Yin
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L21/84 , H01L27/1203
摘要： The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: an SOI wafer comprising a semiconductor substrate, a buried insulation layer, and a semiconductor layer, wherein the buried insulation layer is disposed on the semiconductor substrate, and the semiconductor layer is disposed on the buried insulation layer; a plurality of MOSFETs being formed adjacently to each other in the SOI wafer, wherein each of the MOSFETs comprises a respective backgate being formed in the semiconductor substrate; and a plurality of shallow trench isolations, each of which being formed between respective adjacent MOSFETs to isolate the respective adjacent MOSFETs from each other, wherein the respective adjacent MOSFETs share a common backgate isolation region under the backgates in the semiconductor substrate, and a PNP junction or an NPN junction is formed by the common backgate isolation region and the backgates of the respective adjacent MOSFETs. According to the present disclosure, respective backgates of two adjacent MOSFETs are isolated from each other by the shallow trench isolation. Furthermore, the two adjacent MOSFETs are also isolated from each other by the PNP or NPN junction formed by the respective backgates of the two adjacent MOSFETs and the common backgate isolation. As a result, this device structure has a better insulation effect over the prior art MOSFET and it greatly reduces the possibility of breakthrough.
摘要翻译：本发明提供一种半导体器件及其制造方法。半导体器件包括：SOI晶片，其包括半导体衬底，掩埋绝缘层和半导体层，其中所述掩埋绝缘层设置在所述半导体衬底上，并且所述半导体层设置在所述掩埋绝缘层上; 在SOI晶片中彼此相邻形成的多个MOSFET，其中每个MOSFET包括形成在半导体衬底中的相应后栅; 以及多个浅沟槽隔离，其中每个分别形成在各个相邻的MOSFET之间，以将各个相邻的MOSFET彼此隔离，其中各个相邻的MOSFET共享在半导体衬底中的后栅上的公共后栅极隔离区，以及PNP结或NPN结由相应的相邻MOSFET的公共背栅隔离区和后沿形成。根据本公开，两个相邻MOSFET的相应背板通过浅沟槽隔离彼此隔离。此外，两个相邻的MOSFET也通过由两个相邻MOSFET的相应后沿和公共背栅隔离形成的PNP或NPN结彼此隔离。结果，该器件结构具有比现有技术的MOSFET更好的绝缘效果，并且大大降低了突破的可能性。

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