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91. 发明申请

US20120196410A1 METHOD FOR FABRICATING FIN FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：用于制作Fin场效应晶体管的方法
公开(公告)号：US20120196410A1
公开(公告)日：2012-08-02
申请号：US13017534
申请日：2011-01-31
申请人： Teng-Chun TSAI , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Chin-Cheng Chien
发明人： Teng-Chun TSAI , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Chin-Cheng Chien
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/66545
摘要： A method for fabricating a fin-FET, wherein the method comprises several steps as follows: A substrate is first provided, and a silicon fin is then formed in the substrate. Next a dielectric layer is formed on the silicon fin and the substrate. A poly silicon layer is subsequently formed on the dielectric layer, and the poly silicon layer is then planarized. Subsequently, a poly silicon gate is formed and a portion of the silicon fin is exposed by patterning the planarized poly silicon layer. A source and a drain are separately formed on two opposite sides of the exposed silicon fin adjacent to the poly silicon gate.
摘要翻译：一种制造鳍式FET的方法，其中该方法包括以下几个步骤：首先提供衬底，然后在衬底中形成硅片。接下来，在硅片和衬底上形成介电层。随后在电介质层上形成多晶硅层，然后将多晶硅层平坦化。随后，通过对平坦化的多晶硅层进行构图，形成多晶硅栅极并且使硅片的一部分露出。源极和漏极分别形成在与多晶硅栅极相邻的暴露的硅鳍片的两个相对侧上。

92. 发明申请

US20120115284A1 METHOD FOR MANUFACTURING MULTI-GATE TRANSISTOR DEVICE 有权
标题翻译：制造多栅极晶体管器件的方法
公开(公告)号：US20120115284A1
公开(公告)日：2012-05-10
申请号：US12943015
申请日：2010-11-10
申请人： Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
发明人： Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
IPC分类号： H01L21/336
CPC分类号： H01L29/66795
摘要： A method for manufacturing a multi-gate transistor device includes providing a semiconductor substrate having a first patterned semiconductor layer formed thereon, sequentially forming a gate dielectric layer and a gate layer covering a portion of the first patterned semiconductor layer on the semiconductor substrate, removing a portion of the first patterned semiconductor layer to form a second patterned semiconductor layer, and performing a selective epitaxial growth process to form an epitaxial layer on a surface of the second patterned semiconductor layer.
摘要翻译：一种制造多栅极晶体管器件的方法包括：提供其上形成有第一图案化半导体层的半导体衬底，顺序地形成栅极电介质层和覆盖半导体衬底上的第一图案化半导体层的一部分的栅极层，以形成第二图案化半导体层，并且执行选择性外延生长工艺以在第二图案化半导体层的表面上形成外延层。

93. 发明授权

US07803702B2 Method for fabricating MOS transistors 有权
标题翻译：制造MOS晶体管的方法
公开(公告)号：US07803702B2
公开(公告)日：2010-09-28
申请号：US12189203
申请日：2008-08-11
申请人： Kuo-Chih Lai , Yi-Wei Chen , Nien-Ting Ho , Teng-Chun Tsai
发明人： Kuo-Chih Lai , Yi-Wei Chen , Nien-Ting Ho , Teng-Chun Tsai
IPC分类号： H01L21/28
CPC分类号： H01L21/28518 , H01L29/165 , H01L29/6659 , H01L29/66636
摘要： A method for fabricating metal-oxide transistors is disclosed. First, a semiconductor substrate having a gate structure is provided, in which the gate structure includes a gate dielectric layer and a gate. A source/drain region is formed in the semiconductor substrate, and a cleaning step is performed to fully remove native oxides from the surface of the semiconductor substrate. An oxidation process is conducted to form an oxide layer on the semiconductor substrate and the oxide layer is then treated with fluorine-containing plasma to form a fluorine-containing layer on the surface of the semiconductor substrate. A metal layer is deposited on the semiconductor substrate thereafter and a thermal treatment is performed to transform the metal layer into a silicide layer.
摘要翻译：公开了一种用于制造金属氧化物晶体管的方法。首先，提供具有栅极结构的半导体衬底，其中栅极结构包括栅极介电层和栅极。在半导体衬底中形成源极/漏极区域，并且执行清洁步骤以从半导体衬底的表面中完全去除天然氧化物。进行氧化处理以在半导体衬底上形成氧化物层，然后用含氟等离子体处理氧化物层，以在半导体衬底的表面上形成含氟层。此后，在半导体衬底上沉积金属层，并进行热处理以将金属层转变成硅化物层。

94. 发明授权

US07651960B2 Chemical vapor deposition method preventing particles forming in chamber 有权
标题翻译：化学气相沉积法防止在室内形成颗粒
公开(公告)号：US07651960B2
公开(公告)日：2010-01-26
申请号：US10907857
申请日：2005-04-18
申请人： Neng-Kuo Chen , Teng-Chun Tsai , Hsiu-Lien Liao
发明人： Neng-Kuo Chen , Teng-Chun Tsai , Hsiu-Lien Liao
IPC分类号： C23C16/40 , B05D3/00 , H01L21/469
CPC分类号： C23C16/4404 , H01J37/32082
摘要： Preventing a chemical vapor deposition (CVD) chamber from particle contamination in which a higher low-frequency radio frequency (LFRF) power and longer process time are provided to vacate the chamber and perform a pre-heat process. Following that, a pre-oxide layer is formed on the chamber wall, while a high-frequency radio frequency bias is provided to the chamber. The high-power LFRF is continuously provided to the chamber to sustain the temperature of the chamber, and then a main oxide layer deposition process is performed. The method is able to form an oxide layer of better quality on a CVD chamber wall, so as to solve the particle problem in the prior art. Therefore, yield is improved and the maintenance cost is reduced.
摘要翻译：防止化学气相沉积（CVD）室受到颗粒污染的影响，其中提供较高的低频射频功率（LFRF）功率和较长的处理时间以腾出室并执行预热过程。之后，在室壁上形成预氧化物层，同时向室提供高频射频偏压。大功率LFRF被连续地提供给室以维持室的温度，然后执行主氧化层沉积工艺。该方法能够在CVD室壁上形成更好质量的氧化物层，从而解决现有技术中的颗粒问题。因此，产量提高，维护成本降低。

95. 发明申请

US20090298294A1 METHOD FOR CLEARING NATIVE OXIDE 有权
标题翻译：用于清除原料氧化物的方法
公开(公告)号：US20090298294A1
公开(公告)日：2009-12-03
申请号：US12129978
申请日：2008-05-30
申请人： Yen-Chu Chen , Teng-Chun Tsai , Chien-Chung Huang , Keng-Jen Liu
发明人： Yen-Chu Chen , Teng-Chun Tsai , Chien-Chung Huang , Keng-Jen Liu
IPC分类号： C25F3/30 , H01L21/302
CPC分类号： H01L21/3065 , H01L21/02057 , H01L21/02063
摘要： A method for clearing native oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A clearing process is performed to the substrate using nitrogen trifluoride (NF3) and ammonia (NH3) as a reactant gas, wherein the volumetric flow rate of NF3 is greater than that of NH3.
摘要翻译：描述了清除天然氧化物的方法。提供了一种衬底，包括其中形成有自然氧化物层的暴露部分。使用三氟化氮（NF 3）和氨（NH 3）作为反应气体对基板进行清除处理，其中NF 3的体积流量大于NH 3的体积流量。

96. 发明授权

US07588883B2 Method for forming a gate and etching a conductive layer 有权
标题翻译：形成栅极并蚀刻导电层的方法
公开(公告)号：US07588883B2
公开(公告)日：2009-09-15
申请号：US11382470
申请日：2006-05-09
申请人： Neng-Kuo Chen , Teng-Chun Tsai , Hsiu-Lien Liao
发明人： Neng-Kuo Chen , Teng-Chun Tsai , Hsiu-Lien Liao
IPC分类号： G03F1/00 , H01L21/00
CPC分类号： H01L21/32139 , H01L21/28035 , H01L21/28202 , H01L21/31111 , H01L29/518
摘要： A method for forming a gate and a method for etching a conductive layer are provided. First, a substrate is provided, including a dielectric layer and a conductive layer on its surface in order. Subsequently, a patterned silicon nitride layer is formed on the conductive layer as a hard mask, and the hydrogen concentration of the patterned silicon nitride layer is more than 1022 atoms/cm3. Thereafter, the conductive layer and the dielectric layer are etched utilizing the hard mask as a mask. Finally, an etching solution is utilized to remove the hard mask.
摘要翻译：提供一种形成栅极的方法和蚀刻导电层的方法。首先，在其表面上依次提供包括电介质层和导电层的基板。随后，在导电层上形成图案化氮化硅层作为硬掩模，并且图案化氮化硅层的氢浓度大于1022原子/ cm3。此后，使用硬掩模作为掩模蚀刻导电层和电介质层。最后，使用蚀刻溶液去除硬掩模。

97. 发明申请

US20080305610A1 METHOD FOR MANUFACTURING SHALLOW TRENCH ISOLATION STRUCTURE 审中-公开
标题翻译：制造浅层隔离结构的方法
公开(公告)号：US20080305610A1
公开(公告)日：2008-12-11
申请号：US12190572
申请日：2008-08-12
申请人： Yen-Chu Chen , Hsin-Kun Chu , Teng-Chun Tsai , Chia-Hsi Chen
发明人： Yen-Chu Chen , Hsin-Kun Chu , Teng-Chun Tsai , Chia-Hsi Chen
IPC分类号： H01L21/76
CPC分类号： H01L21/31053
摘要： A method of forming a shallow trench isolation structure includes steps of providing a substrate having a patterned mask layer formed thereon, wherein a trench is located in the substrate and the patterned mask layer exposes the trench. Thereafter, a dielectric layer is formed over the substrate to fill the trench. Then, a main polishing process with a first polishing rate is performed to remove a portion of the dielectric layer. An assisted polishing process is performed to remove the dielectric layer and a portion of the mask layer. The assisted polishing process includes steps of providing a slurry in a first period of time and then providing a solvent and performing a polishing motion of a second polishing rate in a second period of time. The second polishing rate is slower than the first polishing rate. Further, the mask layer is removed.
摘要翻译：形成浅沟槽隔离结构的方法包括提供其上形成有图案化掩模层的衬底的步骤，其中沟槽位于衬底中，并且图案化掩模层暴露沟槽。此后，在衬底上形成电介质层以填充沟槽。然后，执行具有第一抛光速率的主抛光工艺以去除电介质层的一部分。执行辅助抛光处理以去除介电层和掩模层的一部分。辅助抛光方法包括以下步骤：在第一时间段内提供浆料，然后提供溶剂并在第二时间段内执行第二抛光速率的抛光运动。第二抛光速率比第一抛光速度慢。此外，去除掩模层。

98. 发明申请

US20080261402A1 METHOD OF REMOVING INSULATING LAYER ON SUBSTRATE 审中-公开
标题翻译：在基板上去除绝缘层的方法
公开(公告)号：US20080261402A1
公开(公告)日：2008-10-23
申请号：US11736006
申请日：2007-04-17
申请人： Chan Lu , Teng-Chun Tsai , Chih-Yueh Li , Kai-Gin Yang , Chien-Chung Huang , Chia-Hsi Chen , Tzu-Hui Wu
发明人： Chan Lu , Teng-Chun Tsai , Chih-Yueh Li , Kai-Gin Yang , Chien-Chung Huang , Chia-Hsi Chen , Tzu-Hui Wu
IPC分类号： H01L21/302
CPC分类号： H01L21/31053 , H01L21/02065
摘要： A method of removing an insulating layer on a substrate is described, including a first CMP process and a second CMP process performed in sequence, wherein the polishing slurry used in the first CMP process and that used in the second CMP process have substantially the same pH value that exceeds 7.0. A cleaning step is conducted between the first and the second CMP processes to remove a specific substance which would otherwise cause undesired particles to form in the second CMP process.
摘要翻译：描述了去除衬底上的绝缘层的方法，包括依次执行的第一CMP工艺和第二CMP工艺，其中在第一CMP工艺中使用的抛光浆料和在第二CMP工艺中使用的抛光浆料具有基本上相同的pH 价值超过7.0。在第一和第二CMP工艺之间进行清洁步骤以除去否则会在第二CMP工艺中导致不期望的颗粒形成的特定物质。

99. 发明申请

US20080185655A1 SMICONDUCTOR DEVICE, METHOD FOR FABRICATING THEREOF AND METHOD FOR INCREASING FILM STRESS 审中-公开
标题翻译： SMICONDUCTOR DEVICE，METHOD FOR FABRICATING THEREOF METHOD AND METHOD FOR FABRICATING THEWORKING METHOD AND METHOD FOR FABRICATING ANDERIFY AND METHOD FOR INCREASING FILM STRESS
公开(公告)号：US20080185655A1
公开(公告)日：2008-08-07
申请号：US11670584
申请日：2007-02-02
申请人： Shao-Ta Hsu , Teng-Chun Tsai , Neng-Kuo Chen , Hsiu-Lien Liao , Cheng-Han Wu , Wen-Han Hung
发明人： Shao-Ta Hsu , Teng-Chun Tsai , Neng-Kuo Chen , Hsiu-Lien Liao , Cheng-Han Wu , Wen-Han Hung
IPC分类号： H01L21/469 , H01L27/092
CPC分类号： H01L27/092 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/823807 , H01L29/7843
摘要： A method for forming a semiconductor device is provided. The method comprises steps of providing a substrate having a first-conductive-type transistor and a second-conductive-type transistor formed thereon and then forming a stress layer over the substrate to conformally cover the first-conductive-type transistor and the second-conductive-type transistor. A cap layer is formed on the stress layer over the first-conductive-type transistor. A modification process is performed. The cap layer is removed.
摘要翻译：提供一种形成半导体器件的方法。该方法包括以下步骤：提供具有形成在其上的第一导电型晶体管和第二导电型晶体管的衬底，然后在衬底上形成应力层以共形覆盖第一导电型晶体管和第二导电型晶体管型晶体管。在第一导电型晶体管上的应力层上形成覆盖层。执行修改处理。盖层被去除。

100. 发明申请

US20080160786A1 METHOD FOR INCREASING FILM STRESS AND METHOD FOR FORMING HIGH STRESS LAYER 审中-公开
标题翻译：增加膜应力的方法和形成高应力层的方法
公开(公告)号：US20080160786A1
公开(公告)日：2008-07-03
申请号：US11616286
申请日：2006-12-27
申请人： Neng-Kuo Chen , Teng-Chun Tsai , Chien-Chung Huang
发明人： Neng-Kuo Chen , Teng-Chun Tsai , Chien-Chung Huang
IPC分类号： H01L21/469
CPC分类号： H01L29/7843 , H01L21/3185 , H01L21/823807
摘要： A method for forming a high stress layer is provided. According to the method, a substrate is put into a reactor of a PECVD machine and a reaction gas is added into the reactor. Then, an assistant reaction gas which has the molecular weight greater than or equal to the molecular weight of nitrogen gas is added into the reactor. Next, a carrier gas which has the molecular weight smaller than the molecular weight of nitrogen gas is added into the reactor to increase the bombarding efficiency in film deposition. Thereby, the high stress layer is formed on the substrate.
摘要翻译：提供了形成高应力层的方法。根据该方法，将基板放入PECVD机的反应器中，并将反应气体加入到反应器中。然后，将分子量大于等于氮分子量的辅助反应气体加入到反应器中。接下来，将具有小于氮分子量的分子量的载气加入到反应器中，以提高膜沉积中的轰击效率。由此，在基板上形成高应力层。

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