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91. 发明授权

US08797802B2 Method and apparatus for shortened erase operation 有权
标题翻译：用于缩短擦除操作的方法和装置
公开(公告)号：US08797802B2
公开(公告)日：2014-08-05
申请号：US13536555
申请日：2012-06-28
申请人： Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo , Chin-Hung Chang , Chang-Ting Chen
发明人： Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo , Chin-Hung Chang , Chang-Ting Chen
IPC分类号： G11C11/34
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/14 , G11C29/34 , G11C2029/2602
摘要： A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.
摘要翻译：非易失性存储器阵列具有不同持续时间的多个擦除过程。可以通过不同的擦除过程之一来擦除阵列的存储器单元的块。

92. 发明授权

US08677100B2 Serial memory interface for extended address space 有权
标题翻译：用于扩展地址空间的串行存储器接口
公开(公告)号：US08677100B2
公开(公告)日：2014-03-18
申请号：US12813395
申请日：2010-06-10
申请人： Yulan Kuo , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Yulan Kuo , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G06F9/34
CPC分类号： G06F9/30076 , G06F9/30189 , G06F9/342
摘要： An integrated circuit memory device has a memory array and control logic with at least a first addressing mode in which the instruction includes a first instruction code and an address of a first length; and a second addressing mode in which the instruction includes the first instruction code and an address of a second length. The first length of the address is different from the second length of the address.
摘要翻译：集成电路存储器件具有存储器阵列和具有至少第一寻址模式的控制逻辑，其中指令包括第一指令代码和第一长度的地址; 以及第二寻址模式，其中指令包括第一指令代码和第二长度的地址。地址的第一个长度与地址的第二个长度不同。

93. 发明申请

US20130326184A1 MEMORY APPARATUS 有权
标题翻译：记忆装置
公开(公告)号：US20130326184A1
公开(公告)日：2013-12-05
申请号：US13584393
申请日：2012-08-13
申请人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo
发明人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo
IPC分类号： G06F12/00
CPC分类号： G11C7/1072 , G11C7/1066 , G11C7/222 , G11C2207/104
摘要： A memory apparatus includes a host device and a slave device. The host device stores verification data. The slave device includes a memory unit, a control unit, and a logic unit. The control unit drives the memory unit to provide storage data in a data transmission sub-period, and further provides a control signal, indicating the first verification data, in a dummy sub-period. The logic unit provides first preamble data, indicating substantially a same data value as the verification data, in the dummy sub-period in response to the first control signal. The preamble data and the storage data are transmitted according to an internal clock signal. The host device samples the first preamble data according to an external clock signal, and determines whether the external and the internal clock signals are synchronized by comparing the first preamble data and the first verification data.
摘要翻译：存储装置包括主机装置和从装置。主机设备存储验证数据。从设备包括存储器单元，控制单元和逻辑单元。控制单元驱动存储单元以在数据传输子时段中提供存储数据，并且还在虚拟子周期中提供指示第一验证数据的控制信号。逻辑单元响应于第一控制信号，在虚拟子周期中提供与验证数据基本上相同的数据值的第一前同步码数据。前导码数据和存储数据根据内部时钟信号发送。主机设备根据外部时钟信号对第一前同步码数据进行采样，并且通过比较第一前导码数据和第一验证数据来确定外部和内部时钟信号是否被同步。

94. 发明申请

US20120262987A1 METHOD AND APPARATUS FOR LEAKAGE SUPPRESSION IN FLASH MEMORY IN RESPONSE TO EXTERNAL COMMANDS 有权
标题翻译： FLASH存储器中对外部命令的泄漏抑制方法和装置
公开(公告)号：US20120262987A1
公开(公告)日：2012-10-18
申请号：US13308266
申请日：2011-11-30
申请人： Nai-Ping Kuo , Su-Chueh Lo , Kuen-Long Chang , Chun-Hsiung Hung , Chia-Feng Cheng , Ken-Hui Chen , Yu-Chen Wang
发明人： Nai-Ping Kuo , Su-Chueh Lo , Kuen-Long Chang , Chun-Hsiung Hung , Chia-Feng Cheng , Ken-Hui Chen , Yu-Chen Wang
IPC分类号： G11C16/10
CPC分类号： G11C16/3409 , G11C11/5635 , G11C16/0483 , G11C16/14
摘要： Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state.
摘要翻译：本文描述了用于检测和恢复闪存设备中的过擦除存储器单元的技术。在一个实施例中，闪存器件包括包括多个存储单元块的存储器阵列。该设备还包括用于从存储设备外部的源接收命令的命令接口。该装置还包括控制器，其包括响应于该命令执行泄漏抑制处理的逻辑。泄漏抑制处理包括执行软程序操作以增加给定的存储单元块中的一个或多个过擦除存储器单元的阈值电压并建立擦除状态。

95. 发明授权

US08264900B2 Data sensing arrangement using first and second bit lines 有权
标题翻译：使用第一和第二位线的数据传感装置
公开(公告)号：US08264900B2
公开(公告)日：2012-09-11
申请号：US13300141
申请日：2011-11-18
申请人： Yung-Feng Lin , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Yung-Feng Lin , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C7/00
CPC分类号： G11C7/1048 , G11C16/28
摘要： Over-erasure induced noise on a data line in a nonvolatile memory that couples into an adjacent data line is mitigated by using twisted data lines and differential sensing amplifiers. Noise coupled into data lines is compensated by similar noise coupled into reference data lines and cancelled in the differential sensing amplifiers.
摘要翻译：通过使用扭曲的数据线和差分感测放大器来减轻耦合到相邻数据线的非易失性存储器中的数据线上的过度擦除感应噪声。耦合到数据线中的噪声由耦合到参考数据线中的相似噪声补偿并在差分感测放大器中被消除。

96. 发明授权

US08208323B2 Method and apparatus for protection of non-volatile memory in presence of out-of-specification operating voltage 有权
标题翻译：在存在超出规定工作电压的情况下保护非易失性存储器的方法和装置
公开(公告)号：US08208323B2
公开(公告)日：2012-06-26
申请号：US13108768
申请日：2011-05-16
申请人： Chun Hsiung Hung , Kuen Long Chang , Nai Ping Kuo , Ken Hui Chen , Yu Chen Wang
发明人： Chun Hsiung Hung , Kuen Long Chang , Nai Ping Kuo , Ken Hui Chen , Yu Chen Wang
IPC分类号： G11C7/00
CPC分类号： G11C5/143 , G11C16/225 , G11C29/52 , G11C2029/0409
摘要： A method and apparatus for protecting non-volatile memory is described. A write command is processed only when an operating voltage is between specified operating limits and when a data pattern stored in the non-volatile memory is repeatedly read successfully.
摘要翻译：描述了用于保护非易失性存储器的方法和装置。仅当操作电压在指定的操作限制之间以及当存储在非易失性存储器中的数据模式被成功重复读取时，才会处理写入命令。

97. 发明授权

US08041912B2 Memory devices with data protection 有权
标题翻译：具有数据保护功能的内存设备
公开(公告)号：US08041912B2
公开(公告)日：2011-10-18
申请号：US11863254
申请日：2007-09-28
申请人： Yu-Lan Kuo , Chun-Yi Lee , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Yu-Lan Kuo , Chun-Yi Lee , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G06F12/00
CPC分类号： G11C8/20 , G06F21/79 , G11C16/22
摘要： A memory device comprises a memory array, a status register coupled with the memory array, and a security register coupled with the memory array and the status register. The memory array contains a number of memory blocks configured to have independent access control. The status register includes at least one protection bit indicative of a write-protection status of at least one corresponding block of the memory blocks that corresponds to the protection bit. The security register includes at least one register-protection bit. The register-protection bit is programmable to a memory-protection state for preventing a state change of at least the protection bit of the status register. The register-protection bit is configured to remain in the memory-protection state until the resetting of the memory device.
摘要翻译：存储器件包括存储器阵列，与存储器阵列耦合的状态寄存器，以及与存储器阵列和状态寄存器耦合的安全寄存器。存储器阵列包含被配置为具有独立访问控制的多个存储器块。状态寄存器包括至少一个保护位，指示对应于保护位的存储器块的至少一个相应块的写保护状态。安全寄存器包括至少一个寄存器保护位。寄存器保护位可编程为存储器保护状态，以防止至少状态寄存器的保护位的状态改变。寄存器保护位被配置为保持存储器保护状态，直到存储器件的复位。

98. 发明授权

US07965551B2 Method for metal bit line arrangement 有权
标题翻译：金属位线布置方法
公开(公告)号：US07965551B2
公开(公告)日：2011-06-21
申请号：US11703115
申请日：2007-02-07
申请人： Wen-Chiao Ho , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Wen-Chiao Ho , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C11/34
CPC分类号： G11C7/18 , G11C7/02
摘要： A method for metal bit line arrangement is applied to a virtual ground array memory having memory cell blocks. Each memory cell block has memory cells and m metal bit lines, wherein m is a positive integer. The method includes the following steps. First, one of the memory cells is selected as a target memory cell. When the target memory cell is being read, the metal bit line electrically connected to a drain of the target memory cell is a drain metal bit line, and the metal bit line electrically connected to a source is a source metal bit line. Next, a classification of whether the other metal bit lines are charged up when the target memory cell is being read is made. Thereafter, the m metal bit lines are arranged such that charged up metal bit lines are not adjacent to the source metal bit line.
摘要翻译：一种用于金属位线布置的方法被应用于具有存储单元块的虚拟地阵列存储器。每个存储单元块具有存储单元和m个金属位线，其中m是正整数。该方法包括以下步骤。首先，选择一个存储单元作为目标存储单元。当读出目标存储单元时，与目标存储单元的漏极电连接的金属位线是漏极金属位线，与源极电连接的金属位线是源极金属位线。接着，对目标存储单元进行读取时，分类其他金属位线是否被充电。此后，m个金属位线布置成使得带电的金属位线不与源极金属位线相邻。

99. 发明申请

US20100027339A1 PAGE BUFFER AND METHOD OF PROGRAMMING AND READING A MEMORY 有权
标题翻译：页面缓冲区和编程和读取存储器的方法
公开(公告)号：US20100027339A1
公开(公告)日：2010-02-04
申请号：US12182245
申请日：2008-07-30
申请人： Wen-Chiao HO , Chin-Hung CHANG , Kuen-Long CHANG , Chun-Hsiung HUNG
发明人： Wen-Chiao HO , Chin-Hung CHANG , Kuen-Long CHANG , Chun-Hsiung HUNG
IPC分类号： G11C16/04 , G11C7/00
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5642 , G11C2211/5621 , G11C2211/5646 , G11C2216/14
摘要： A page buffer and method of programming and reading a memory are provided. The page buffer includes a first latch, a second latch, a data change unit and a program control unit. The first latch includes a first terminal for loading data of the lower page and the upper page. The second latch includes a first terminal for storing the data of the lower page and the upper page from the first latch. The data change unit is coupled to a second terminal of the first latch for changing a voltage of the second terminal of the first latch to a low level. The program control unit is coupled to the first terminal of the second latch and the cells, and controlled by the voltage of the first terminal of the first latch for respectively programming the data of the lower page and the upper page to a target cell.
摘要翻译：提供了一种页面缓冲器和编程和读取存储器的方法。页面缓冲器包括第一锁存器，第二锁存器，数据改变单元和程序控制单元。第一锁存器包括用于加载下页和上页的数据的第一终端。第二锁存器包括用于存储来自第一锁存器的下页数据和上页数据的第一终端。数据改变单元耦合到第一锁存器的第二端子，用于将第一锁存器的第二端子的电压改变到低电平。程序控制单元耦合到第二锁存器和单元的第一端子，并且由第一锁存器的第一端子的电压控制，以分别将下页数据和上部页面的数据编程到目标单元。

100. 发明授权

US07652512B2 Clock synchronizing circuit 有权
标题翻译：时钟同步电路
公开(公告)号：US07652512B2
公开(公告)日：2010-01-26
申请号：US12027285
申请日：2008-02-07
申请人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Wen-Chiao Ho , Chin-Hung Chang , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： H03L7/00
CPC分类号： H03K5/135 , H03K5/06 , H03K2005/00195
摘要： A clock synchronizing circuit applied in a SMD block is provided. The clock synchronizing circuit includes a number of stages of clock synchronizing units. The clock synchronizing circuit can achieve the purpose of clock synchronizing by using a novel circuit design of the forward delay unit, the mirror control unit or the backward delay unit in each stage of clock synchronizing unit or by using a short-pulse generation circuit to generate a short pulse for triggering out an output clock of each stage of forward delay unit.
摘要翻译：提供了应用在SMD块中的时钟同步电路。时钟同步电路包括多个时钟同步单元级。时钟同步电路可以通过使用时钟同步单元的每一级中的前向延迟单元，反射镜控制单元或后向延迟单元的新颖的电路设计来实现时钟同步的目的，或者通过使用短脉冲发生电路来产生用于触发前级延迟单元各级的输出时钟的短脉冲。

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