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91. 发明申请

US20140167110A1 PARTIAL POLY AMORPHIZATION FOR CHANNELING PREVENTION 审中-公开
标题翻译：部分多用途通道预防措施
公开(公告)号：US20140167110A1
公开(公告)日：2014-06-19
申请号：US14188022
申请日：2014-02-24
申请人： GLOBAL FOUNDRIES Inc.
发明人： Peter JAVORKA , Glyn BRAITHWAITE
IPC分类号： H01L29/78 , H01L27/092 , H01L29/49
CPC分类号： H01L29/7848 , H01L21/26506 , H01L21/28052 , H01L21/823814 , H01L21/823828 , H01L27/092 , H01L29/4933 , H01L29/66507 , H01L29/66583 , H01L29/78
摘要： Semiconductor devices are formed without zipper defects or channeling and through-implantation and with different silicide thicknesses in the gates and source/drain regions, Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region in the substrate on each side of the gate, forming a wet cap fill layer on the source/drain region on each side of the gate, removing the nitride cap from the gate, and forming an amorphized layer in a top portion of the gate. Embodiments include forming the amorphized layer by implanting low energy ions.
摘要翻译：半导体器件在栅极和源极/漏极区域中形成没有拉链缺陷或沟槽和贯穿植入以及不同的硅化物厚度，实施例包括在衬底上形成栅极，在栅极上形成氮化物帽，形成源极/漏极区域在栅极的每一侧的衬底中，在栅极的每一侧上的源极/漏极区域上形成湿盖填充层，从栅极去除氮化物帽，并在栅极的顶部部分形成非晶化层。实施例包括通过注入低能离子形成非晶化层。

92. 发明申请

US20180269868A1 CIRCUIT TUNING SCHEME FOR FDSOI 审中-公开
公开(公告)号：US20180269868A1
公开(公告)日：2018-09-20
申请号：US15459867
申请日：2017-03-15
申请人： GLOBAL FOUNDRIES Inc.
发明人： Abdellatif Bellaouar , Arul Balasubramaniyan
IPC分类号： H03K17/16 , H01L27/092 , H01L29/78 , H01L29/06 , H03K3/012
摘要： A method of circuit tuning, including: applying a first positive voltage and a second positive voltage to a circuit structure, the circuit structure including a p-type metal-oxide semiconductor (PMOS) device with a flipped well transistor and an n-type metal-oxide semiconductor (NMOS) device; adjusting a first threshold voltage in response to the first positive voltage being applied to a p-well region of the NMOS device and adjusting a second threshold voltage in response to the second positive voltage being applied to the p-well region of the PMOS device; and compensating the first threshold voltage and the second threshold voltage through a backgate of the PMOS device and the NMOS device relative to a same common mode voltage.

93. 发明申请

US20160357898A1 DESIGN OF TEMPERATURE-COMPLIANT INTEGRATED CIRCUITS 有权
标题翻译：温度合并集成电路设计
公开(公告)号：US20160357898A1
公开(公告)日：2016-12-08
申请号：US14728100
申请日：2015-06-02
申请人： GLOBAL FOUNDRIES INC.
发明人： James M. Johnson , Sungjae Lee , Lan Luo , Scott K. Springer
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/80
摘要： Aspects of the present disclosure include a computer-implemented method for designing a temperature-compliant integrated circuit (IC). The method can include: calculating a thermal resistance of an IC layout, the IC layout having an area-dependent thermal conductance, a fin thermal conductance, and a gate thermal conductance each based on a device geometry of a plurality of transistors in the IC layout; calculating a self-heating temperature as directly proportional to the thermal resistance; comparing the self-heating temperature with a threshold temperature; in response to the self-heating temperature exceeding the threshold temperature, automatically modifying the device geometry of the IC layout to reduce at least one of the area term and the perimeter term, thereby reducing the self-heating temperature of the IC layout; and designing the temperature-compliant IC layout by repeating the calculating and automatically modifying steps until the self-heating temperature does not exceed the threshold temperature.
摘要翻译：本公开的方面包括用于设计温度兼容集成电路（IC）的计算机实现的方法。该方法可以包括：计算IC布局的热电阻，IC布局具有面积依赖性热导率，翅片热导率和栅极热导，其各自基于IC布局中的多个晶体管的器件几何形状 ; 计算自热温度与热阻成正比; 将自加热温度与阈值温度进行比较; 响应于自加热温度超过阈值温度，自动修改IC布局的器件几何形状以减少面积项和周边项中的至少一个，从而降低IC布局的自加热温度; 并通过重复计算和自动修改步骤来设计温度兼容的IC布局，直到自加热温度不超过阈值温度。

94. 发明授权

US09484252B2 Integrated circuits including selectively deposited metal capping layers on copper lines and methods for fabricating the same 有权
标题翻译：集成电路包括铜线上的选择性沉积的金属覆盖层及其制造方法
公开(公告)号：US09484252B2
公开(公告)日：2016-11-01
申请号：US14150428
申请日：2014-01-08
申请人： GLOBAL FOUNDRIES, Inc.
发明人： Moosung Chae , Larry Zhao
IPC分类号： H01L21/44 , H01L21/768 , H01L23/532 , H01L23/528 , H01L21/3213
CPC分类号： H01L21/76852 , H01L21/32136 , H01L21/32139 , H01L21/76885 , H01L23/5283 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes selectively depositing a metal capping layer on first sidewalls of a copper line while leaving exposed portions of a dielectric layer that are laterally adjacent to the copper line exposed. An ILD layer is deposited overlying the metal capping layer and the exposed portions of the dielectric layer.
摘要翻译：提供了用于制造集成电路的集成电路和方法。在一个示例中，制造集成电路的方法包括在铜线的第一侧壁上选择性地沉积金属覆盖层，同时留下与暴露的铜线横向相邻的电介质层的暴露部分。覆盖金属覆盖层和电介质层的暴露部分上的ILD层被沉积。

95. 发明申请

US20160071774A1 OPPOSITE POLARITY BORDERLESS REPLACEMENT METAL CONTACT SCHEME 有权
标题翻译： OPPOSITE极地无边界替代金属接触方案
公开(公告)号：US20160071774A1
公开(公告)日：2016-03-10
申请号：US14482529
申请日：2014-09-10
申请人： GLOBAL FOUNDRIES Inc.
发明人： Andy Chih-Hung Wei , Guillaume Bouche , Huy M. Cao , Jing Wan
IPC分类号： H01L21/8234 , H01L21/311 , H01L27/088 , H01L21/308
CPC分类号： H01L21/823475 , H01L21/3081 , H01L21/3085 , H01L21/3086 , H01L21/31111 , H01L21/31144 , H01L21/76801 , H01L21/76802 , H01L21/76808 , H01L21/76877 , H01L21/76897 , H01L21/823437 , H01L27/088
摘要： An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A set of masks is formed over a portion of the semiconductor structure. Each mask in this set of masks covers at least one source/drain (s/d) contact location. An oxide layer is removed from remainder portions of the semiconductor structure that are not covered by the set of masks. Then an opposite-mask fill layer is formed in the remainder portions from which the oxide layer was removed. The oxide layer is then removed from the remainder of the semiconductor structure, i.e., the portion previously covered by the set of masks and contacts are formed to the at least s/d contact location in the recesses formed by the removal of the remainder of the oxide layer.
摘要翻译：提供了一种在半导体结构中提供改进的晶体管触点的改进的半导体结构和制造方法。在半导体结构的一部分上形成一组掩模。这组掩模中的每个掩模覆盖至少一个源/漏（s / d）接触位置。从半导体结构的未被该组掩模覆盖的其余部分去除氧化物层。然后在除去氧化物层的剩余部分中形成相对掩模填充层。然后从半导体结构的其余部分去除氧化物层，即，先前被该组掩模和触点覆盖的部分形成在通过去除其余部分形成的凹部中的至少s / d接触位置氧化层。

96. 发明申请

US20150364372A1 DOUBLE SELF-ALIGNED VIA PATTERNING 有权
标题翻译：双向自对准通过方式
公开(公告)号：US20150364372A1
公开(公告)日：2015-12-17
申请号：US14837865
申请日：2015-08-27
申请人： International Business Machines Corporation , GLOBAL FOUNDRIES Inc.
发明人： Hsueh-Chung Chen , Yongan Xu , Yunpeng Yin , Ailian Zhao
IPC分类号： H01L21/768 , H01L21/311 , H01L21/033
CPC分类号： H01L21/76802 , H01L21/0332 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76811 , H01L21/76816 , H01L21/76897 , H01L21/76898
摘要： A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer.
摘要翻译：一种包括在衬底上形成五层硬掩模的方法，所述五层硬掩模包括在第二硬掩模层上方的第一硬掩模层; 在第一硬掩模层中形成沟槽图案; 将第一通孔条图案从五层硬掩模上方的第一光致抗蚀剂层转移到第二硬掩模层中，产生第一通孔图案，第二硬掩模层中的第一通孔图案与沟槽图案重叠并且在双面通过第一个硬掩模层中的沟槽图案; 以及将所述第一通孔图案从所述第二硬掩模层转移到所述衬底中，从而产生自对准的通孔，所述自对准通孔开口通过所述第二硬掩模层中的所述第一通孔图案在所有侧面上自对准。

97. 发明申请

US20150339428A1 MASK-AWARE ROUTING AND RESULTING DEVICE 有权
标题翻译：掩蔽路由和结果设备
公开(公告)号：US20150339428A1
公开(公告)日：2015-11-26
申请号：US14286395
申请日：2014-05-23
申请人： Global Foundries Inc.
发明人： Lei YUAN , Jongwook KYE , Harry J. LEVINSON
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5081
摘要： Methods for routing a metal routing layer based on mask design rules and the resulting devices are disclosed. Embodiments may include laying-out continuous metal lines in a semiconductor design layout, and routing, by a processor, a metal routing layer using the continuous metal lines according to placement of cut or block masks based on cut or block mask design rules.
摘要翻译：公开了基于掩模设计规则和所得到的设备来布线金属路由层的方法。实施例可以包括在半导体设计布局中布置连续金属线，以及根据切割或块掩模设计规则，根据切割或块掩模的放置，利用处理器路由使用连续金属线的金属布线层。

98. 发明申请

US20150235957A1 INTEGRATED CIRCUITS WITH IMPROVED CONTACT STRUCTURES 有权
标题翻译：具有改进接触结构的集成电路
公开(公告)号：US20150235957A1
公开(公告)日：2015-08-20
申请号：US14695965
申请日：2015-04-24
申请人： GLOBAL FOUNDRIES, Inc.
发明人： Xunyuan Zhang , Xuan Lin , Vimal Kamineni
IPC分类号： H01L23/532 , H01L23/528
CPC分类号： H01L23/53266 , H01L21/28562 , H01L21/31144 , H01L21/32134 , H01L21/76814 , H01L21/76843 , H01L21/76849 , H01L23/485 , H01L23/528 , H01L23/53209 , H01L23/53228 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Integrated circuits with improved contact structures are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate disposed with a device therein and/or thereon. The integrated circuit includes a contact structure in electrical contact with the device. The contact structure includes a plug metal and a barrier layer, and the barrier layer is selected from fluorine-free tungsten (FFW), tungsten carbide, and tungsten nitride. The integrated circuit further includes a dielectric material overlying the semiconductor substrate. Also, the integrated circuit includes an interconnect formed within the dielectric material and in electrical contact with the contact structure.
摘要翻译：提供了具有改进的接触结构的集成电路。在示例性实施例中，集成电路包括在其中和/或其上设置有设备的半导体衬底。集成电路包括与器件电接触的接触结构。接触结构包括插塞金属和阻挡层，阻挡层选自无氟钨（FFW），碳化钨和氮化钨。集成电路还包括覆盖半导体衬底的电介质材料。此外，集成电路包括形成在电介质材料内并与接触结构电接触的互连。

99. 发明申请

US20150228656A1 REPLACEMENT GATE COMPATIBLE eDRAM TRANSISTOR WITH RECESSED CHANNEL 审中-公开
标题翻译：更换栅格兼容eDRAM晶体管带有通道
公开(公告)号：US20150228656A1
公开(公告)日：2015-08-13
申请号：US14175849
申请日：2014-02-07
申请人： GLOBAL FOUNDRIES Inc.
发明人： Till SCHLOESSER , Peter BAARS , Frank JAKUBOWSKI
IPC分类号： H01L27/108 , H01L29/78 , H01L29/49 , H01L29/45 , H01L29/423 , H01L29/51
CPC分类号： H01L27/10823 , H01L27/10876 , H01L27/10894 , H01L27/10897 , H01L29/42356 , H01L29/4236 , H01L29/42364 , H01L29/42372 , H01L29/456 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66621 , H01L29/78 , H01L29/7833 , H01L29/7848
摘要： An eDRAM is fabricated including high performance logic transistor technology and ultra low leakage DRAM transistor technology. Embodiments include forming a recessed channel in a substrate, forming a first gate oxide to a first thickness lining the channel and a second gate oxide to a second thickness over a portion of an upper surface of the substrate, forming a first polysilicon gate in the recessed channel and overlying the recessed channel, forming a second polysilicon gate on the second gate oxide, forming spacers on opposite sides of each of the first and second polysilicon gates, removing the first and second polysilicon gates forming first and second cavities, forming a high-k dielectric layer on the first and second gate oxides, and forming first and second metal gates in the first and second cavities, respectively.
摘要翻译：一种eDRAM被制造成包括高性能逻辑晶体管技术和超低泄漏DRAM晶体管技术。实施例包括在衬底中形成凹陷通道，在衬底的上表面的一部分上形成第一栅极氧化物至衬底通道的第一厚度和形成第二厚度的第二栅极氧化物，在凹陷部分中形成第一多晶硅栅极在所述第二栅极氧化物上形成第二多晶硅栅极，在所述第一和第二多晶硅栅极中的每一个的相对侧上形成间隔物，去除形成第一和第二空腔的第一和第二多晶硅栅极， k电介质层，并且分别在第一和第二腔中形成第一和第二金属栅极。

100. 发明申请

US20150214149A1 E-FUSE STRUCTURE WITH METHODS OF FUSING THE SAME AND MONITORING MATERIAL LEAKAGE 有权
标题翻译：电熔炉结构与其相同方法和监测材料泄漏
公开(公告)号：US20150214149A1
公开(公告)日：2015-07-30
申请号：US14165039
申请日：2014-01-27
申请人： Internatioal Business Machines Corporation , Samsung Electronics Co., Ltd. , GLOBAL FOUNDRIES, Inc.
发明人： Dan Moy , Kwon O Sung , Kihwang Son , Xiaoqiang Zhang
IPC分类号： H01L23/525 , G01R31/02 , H01L23/367 , H01L21/321 , H01L23/532 , H01L23/522
CPC分类号： H01L23/5256 , G01R31/2858 , H01L21/321 , H01L22/12 , H01L22/34 , H01L23/367 , H01L23/3677 , H01L23/5226 , H01L23/528 , H01L23/53214 , H01L23/53228 , H01L23/53257 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure generally provides for an e-fuse structure and corresponding method for fusing the same and monitoring material leakage. The e-fuse structure can include a metal dummy structure and an electrical fuse link substantially aligned with a portion of the metal dummy structure, wherein the metal dummy structure cools at least part of the electrical fuse link in response to an electric current passing through the electrical fuse link.
摘要翻译：本公开通常提供电熔丝结构和相应的熔化相同方法并监测材料泄漏。 e熔丝结构可以包括金属虚设结构和基本上与金属虚设结构的一部分对准的电熔丝链，其中金属虚拟结构响应于通过电熔丝的电流冷却电熔丝链的至少一部分电熔丝连接。

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