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91. 发明申请

US20170104461A1 ON-CHIP RESISTOR DIVIDER COMPENSATION WITH A 2VRMS INPUT 审中-公开
公开(公告)号：US20170104461A1
公开(公告)日：2017-04-13
申请号：US15385717
申请日：2016-12-20
申请人： Avnera Corporation
发明人： Ali Hadiashar , Wai Laing Lee
IPC分类号： H03F3/183 , H03F3/45
CPC分类号： H03F3/183 , H03F1/26 , H03F3/187 , H03F3/45475 , H03F3/45941 , H03F3/45968 , H03F3/68 , H03F2200/03 , H03F2200/372 , H03F2203/45418 , H03F2203/45522 , H03F2203/45531
摘要： A new compensation system for an audio input reduces noise by matching feedback ratios in the positive and negative paths. A variable resistance network allows for fine control of resistance trimming in one of the signal paths, which allows for compensation between tolerance of resistors that are external to an integrated circuit and those that are internal to the integrated circuit.

92. 发明授权

US09520893B1 Architecture for ensuring monotonicity in a digital-to-analog converter 有权
标题翻译：用于确保数模转换器中单调性的架构
公开(公告)号：US09520893B1
公开(公告)日：2016-12-13
申请号：US15067500
申请日：2016-03-11
申请人： AVNERA CORPORATION
发明人： Christopher D. Nilson
IPC分类号： H03M1/06 , H03M1/66 , G05F3/26 , H03M1/00 , H03M1/74 , H03M1/12
CPC分类号： H03M1/747 , G05F3/262 , H03M1/00 , H03M1/12 , H03M1/68
摘要： A current-mode, digital-to-analog converter (DAC) configured to convert a digital word input having j bits to an analog signal. The DAC has 2j current sources, an output node, a current divider, a first switch, and a second switch. Each of the 2j current sources is configured to produce a current having a value I0. The current divider has a programmable divide ratio, d, where 1/d is between 0 and 1. The first switch is configured to selectively couple 2j−1 of the 2j current sources to the output node. One of the 2j current sources is not coupled to the output node. The second switch is configured to selectively couple each of the 2j current sources to the current divider. This architecture ensures that the fundamental transform of input code to output current always has a slope that does not change from positive to negative or from negative to positive.
摘要翻译：电流模式的数模转换器（DAC），被配置为将具有j位的数字字输入转换为模拟信号。 DAC具有2j电流源，输出节点，分流器，第一开关和第二开关。每个2j电流源被配置为产生具有值I0的电流。电流分压器具有可编程分频比d，其中1 / d在0和1之间。第一开关被配置为选择性地将2j电流源的2j-1耦合到输出节点。 2j电流源中的一个未耦合到输出节点。第二开关被配置为选择性地将2j电流源中的每一个耦合到电流分配器。这种架构确保输入代码对输出电流的基本变换总是具有不会从正变化到负变化或从负变为正的斜率。

93. 发明申请

US20160140983A1 RATE CONVERTOR 有权
标题翻译：速率转换器
公开(公告)号：US20160140983A1
公开(公告)日：2016-05-19
申请号：US14857681
申请日：2015-09-17
申请人： AVNERA CORPORATION
发明人： Xudong Zhao
IPC分类号： G10L21/043 , G10L19/008 , G10L21/0232 , G10L19/02 , G10L19/24 , G10L21/0224
CPC分类号： H03H17/0628 , G10L19/00 , G10L19/24 , G10L21/0316 , G10L21/0356 , G10L2019/001 , H03H17/028 , H03M5/00 , H03M7/00 , H03M13/00 , H03M13/27 , H03M13/33
摘要： Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.
摘要翻译：本发明的实施例可以用于实现速率转换器，其包括：正向（音频）路径中的6个信道，每个信道具有每信道24位信号路径，110dB的端到端SNR，全部在 20 Hz至20 KHz带宽。实施例还可以用于实现速率转换器，其具有：在反向路径中的2个信道，例如用于语音信号，每信道16位信号路径，93dB的端到端SNR，均在20Hz至20 KHz带宽。速率转换器可以包括诸如8,11.025,12,16,22.05,24,34,44,48和96KHz的采样率。此外，根据实施例的速率转换器可以包括低功率模式的门控时钟以节省功率。

94. 发明申请

US20140219490A1 ACOUSTIC LAYER IN MEDIA DEVICE PROVIDING ENHANCED AUDIO PERFORMANCE 有权
标题翻译：在提供增强音频性能的媒体设备中的声音层
公开(公告)号：US20140219490A1
公开(公告)日：2014-08-07
申请号：US14231664
申请日：2014-03-31
申请人： Avnera Corporation
发明人： Patrick A. Quinn , Robert C. Proebstel , Manpreet S. Khaira , Thomas Irrgang , Nigel D. Waites , Ian J. Myles
IPC分类号： H04R1/32
CPC分类号： H04R1/32 , H04R1/026 , H04R1/2803 , H04R3/005 , H04R29/00 , H04R2225/33 , H04R2400/03 , H04R2420/07
摘要： An acoustic layer is added to a laptop-type personal computing device, comprising: enclosing walls, optionally—one or more microphones, a signal processing device, at least one audio transducer, and an acoustic waveguide. The acoustic layer adjoins one or more internal areas of a laptop-type device. The signal processing device receives an internal signal from a laptop-type device. The signal processing device provides a directive sound enhancement of the audio input signals based on room acoustics, such as reverberation, echo, noise, delay, frequency response, and/or speaker-positional information that is determined by the signal processing device. The audio transducer device generates an audible audio output in response to an audio signal output from the signal processing device. The acoustic waveguide receives the audible audio output and generates an enhanced bass audio output from the acoustic waveguide.
摘要翻译：声学层被添加到笔记本电脑型个人计算设备中，包括：封闭墙壁，可选地一个或多个麦克风，信号处理设备，至少一个音频换能器和声波导。声学层邻接膝上型设备的一个或多个内部区域。信号处理装置从笔记本电脑型装置接收内部信号。信号处理装置基于由信号处理装置确定的诸如混响，回波，噪声，延迟，频率响应和/或扬声器位置信息的房间声学来提供音频输入信号的指令声音增强。音频换能器装置响应于从信号处理装置输出的音频信号产生可听音频输出。声波导接收可听音频输出，并从声波导产生增强的低音音频输出。

95. 发明授权

US11677383B2 Rate converter 有权
公开(公告)号：US11677383B2
公开(公告)日：2023-06-13
申请号：US16296669
申请日：2019-03-08
申请人： AVNERA CORPORATION
发明人： Xudong Zhao
IPC分类号： G10L21/0316 , H03H17/06 , H03M13/33 , H03M13/00 , H03M13/27 , H03M7/00 , H03M5/00 , G10L21/0356 , H03H17/02 , G10L19/24 , G10L19/00
CPC分类号： H03H17/0628 , G10L21/0316 , G10L21/0356 , H03H17/028 , H03M5/00 , H03M7/00 , H03M13/00 , H03M13/27 , H03M13/33 , G10L19/00 , G10L19/24 , G10L2019/001
摘要： Embodiments of the invention may be used to implement a rate converter that includes: 6 channels in forward (audio) path, each channel having a 24-bit signal path per channel, an End-to-end SNR of 110 dB, all within the 20 Hz to 20 KHz bandwidth. Embodiment may also be used to implement a rate converter having: 2 channels in a reverse path, such as for voice signals, 16-bit signal path per channel, an End-to-end SNR of 93 dB, all within 20 Hz to 20 KHz bandwidth. The rate converter may include sample rates such as 8, 11.025, 12, 16, 22.05, 24, 32 44.1, 48, and 96 KHz. Further, rate converters according to embodiments may include a gated clock in low-power mode to conserve power.

96. 发明授权

US11611822B2 Earbud operation during earbud insertion detection 有权
公开(公告)号：US11611822B2
公开(公告)日：2023-03-21
申请号：US17806295
申请日：2022-06-10
申请人： AVNERA CORPORATION
发明人： Michael Jon Wurtz , Amit Kumar , Jiajin An
IPC分类号： H04R1/10 , H04R29/00 , H04R3/04 , H04R1/08 , G10K11/178 , H03F13/00 , H03G7/00 , H03F3/181 , H03F3/60
摘要： A method of operating a headphone configured to be removed from and placed in close proximity to a user's ear can include generating an input signal by an input signal generating device. The method can also include determining whether an insertion event has occurred based on the generated input signal and causing the headphone to operate in 5 a low power mode responsive to an absence of an insertion event determination after a first period of time. The method can also include causing the headphone to operate in an ultra-low power mode responsive to the absence of an insertion event determination after a second period of time that occurs after the first period of time, the ultra-low power mode having a lower power consumption than the low power mode.

97. 发明授权

US11366633B2 Automatic playback time adjustment 有权
公开(公告)号：US11366633B2
公开(公告)日：2022-06-21
申请号：US16017800
申请日：2018-06-25
申请人： AVNERA CORPORATION
发明人： Shawn O'Connor , Eric Sorensen , Manpreet S. Khaira , Sydney Newton
IPC分类号： G06F3/16 , H04R1/10 , H04R5/033
摘要： An apparatus can include an audio playback device configured to provide an audio output to a user, and a controller configured to: receive an initial playback position within the audio output; determine that an off-ear event has occurred; identify a time corresponding to the off-ear event; instruct the audio playback device to pause the audio output at the identified time; and calculate a new playback position within the audio output based at least in part on the identified time.

98. 发明授权

US10867605B2 Earbud having audio recognition neural net processor architecture 有权
公开(公告)号：US10867605B2
公开(公告)日：2020-12-15
申请号：US16399757
申请日：2019-04-30
申请人： AVNERA CORPORATION
发明人： Christopher James O'Connor
IPC分类号： G10L15/22 , G06N3/04 , G06F17/16 , G10L15/16 , G06F17/14 , H04R1/10 , G10L15/08
CPC分类号： G10L15/22 , G06F17/142 , G06F17/16 , G06N3/04 , G10L15/16 , H04R1/105 , H04R1/1008 , H04R1/1016 , H04R1/1041 , H04R1/1091 , G10L2015/088 , G10L2015/223
摘要： A system for operating an earbud can include a primary processor to control the earbud and operate in a low-power state, a microphone to receive an input, a casing having a speaker configured to provide audio output from the primary processor to a user's ear, the casing being configured to maintain a position in a user's ear canal to maintain a position of the speaker within the user's ear, a listening sub-system to convert the input into an output signal, and a neural net processor to receive the output signal from the listening sub-system and determine whether to generate a wake signal based on the received output signal.

99. 发明授权

US10650797B2 Real-time acoustic processor 有权
公开(公告)号：US10650797B2
公开(公告)日：2020-05-12
申请号：US16404514
申请日：2019-05-06
申请人： Avnera Corporation
发明人： Amit Kumar
IPC分类号： G10K11/175 , G10K11/178
摘要： The disclosure includes an acoustic processing network comprising a Digital Signal Processor (DSP) operating at a first frequency and a Real-Time Acoustic Processor (RAP) operating at a second frequency higher than the first frequency. The DSP receives a noise signal from at least one microphone. The DSP then generates a noise filter based on the noise signal. The RAP receives the noise signal from the microphone and the noise filter from the DSP. The RAP then generates an anti-noise signal based on the noise signal and the noise filter for use in Active Noise Cancellation (ANC).

100. 发明授权

US10574254B2 Hybrid flash architecture of successive approximation register analog to digital converter 有权
公开(公告)号：US10574254B2
公开(公告)日：2020-02-25
申请号：US16173398
申请日：2018-10-29
申请人： Avnera Corporation
发明人： Wai Lee , Jianping Wen , Garry N. Link
IPC分类号： H03M1/46 , H03M1/44 , H03M1/10 , H03M1/18
摘要： The disclosure includes a mechanism for mitigating electrical current leakage in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by using a Flash ADC in conjunction with the SAR ADC. A sequence controller in the SAR ADC uses the output of the Flash ADC to control a switch array. Depending on the output of the Flash ADC, the sequence controller can control the switch array to couple at least one capacitor in the capacitor network of the SAR ADC to a voltage that reduces charge leakage in the SAR ADC. The voltage may be a pre-defined positive or negative reference voltage.

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