专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

91. 发明授权

US5266829A Electrically-programmable low-impedance anti-fuse element 失效
标题翻译：电子可编程低阻抗保险丝元件
公开(公告)号：US5266829A
公开(公告)日：1993-11-30
申请号：US910422
申请日：1992-07-08
申请人： Esmat Z. Hamdy , Amr M. Mohsen , John L. McCullum , Shih-Ou Chen , Steve S. Chiang
发明人： Esmat Z. Hamdy , Amr M. Mohsen , John L. McCullum , Shih-Ou Chen , Steve S. Chiang
IPC分类号： H01L23/525 , H01L27/06 , H01L27/08
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011
摘要： Electrically-programmable low-impedance anti-fuses are disclosed having capacitor-like structure with very low leakage before programming and a low resistance after programming. The electrically-programmable low-impedance antifuses of the present invention include a first conductive electrode which may be formed as a diffusion region in a semiconductor substrate or may be formed from a semiconductor material, such as polysilicon, located above and insulated from the substrate. A dielectric layer, which, in a preferred embodiment includes a first layer of silicon dioxide, a second layer of silicon nitride and a third layer of silicon dioxide, is disposed over the first electrode. A second electrode is formed over the dielectric layer from a semiconductor material such as polysilicon, or a metal having a barrier metal underneath. At least one of the two electrodes of each anti-fuse is highly-doped or implanted with arsenic such that high concentrations of arsenic exist at the interface between the electrode and the dielectric layer. This arsenic will combine with other material and flow into the anti-fuse filament after programmed to form a low resistance controllable anti-fuse link. Circuitry is provided which allows the anti-fuse of the present invention to be programmed by application of a suitable programming voltage to input-output pins of the integrated circuit containing the antifuse. Where more than one anti-fuse is to be programmed using the programming voltage applied at the input-output terminals, other additional input-output terminals may serve as address inputs to specify the anti-fuse to be programmed.
摘要翻译：公开了电可编程的低阻抗抗熔丝，其具有电容器状结构，在编程之前具有非常低的泄漏并且在编程之后具有低电阻。本发明的电可编程低阻抗反熔丝包括可以形成为半导体衬底中的扩散区域的第一导电电极，或者可以由位于衬底上方并与衬底绝缘的半导体材料（例如多晶硅）形成。在优选实施例中，介电层包括第一层二氧化硅，第二层氮化硅和第三层二氧化硅，设置在第一电极上。第二电极由诸如多晶硅的半导体材料或在其下方具有阻挡金属的金属在电介质层上形成。每个反熔丝的两个电极中的至少一个被高度掺杂或注入砷，使得高浓度的砷存在于电极和电介质层之间的界面处。这种砷将与其他材料结合并经编程后流入反熔丝，以形成低电阻可控的反熔丝链。提供电路，其允许通过对包含反熔丝的集成电路的输入输出引脚施加合适的编程电压来编程本发明的反熔丝。在使用输入 - 输出端子上施加的编程电压对多个反熔丝进行编程的情况下，其他附加输入 - 输出端可用作地址输入，以指定要编程的反熔丝。

92. 发明授权

US5223792A Testability architecture and techniques for programmable interconnect architecture 失效
标题翻译：可测试架构和可编程互连架构技术
公开(公告)号：US5223792A
公开(公告)日：1993-06-29
申请号：US891969
申请日：1992-05-26
申请人： Khaled A. El-Ayat , Jia-Hwang Chang
发明人： Khaled A. El-Ayat , Jia-Hwang Chang
IPC分类号： G01R31/28 , G01R31/3185 , H03K19/177
CPC分类号： H03K19/17764 , G01R31/2884 , G01R31/318516 , H03K19/17704 , H03K19/1778
摘要： Apparatus for testing for defects in the form of ohmic leakage in an antifuse element disposed between first and second conductors in an integrated circuit prior to formation of electronic circuits by a user, includes circuitry, responsive to signals provided to the integrated circuit from an external source, for temporarily connecting together a first group of the conductors to form a circuit path to the first conductor during a first time period. Circuitry, responsive to signals provided to the integrated circuit from an external source, is provided to temporarily connect together a second group of the conductors to form a circuit path to the second conductor during the first time period. Circuitry is provided to place an electrical charge onto the first conductor during a second time period within the first time period such that a selected dynamic first voltage potential is placed on the first conductor. Circuitry is provided to drive the second conductor to a second voltage potential different from the selected dynamic first voltage potential during a third time period subsequent to the second time period and within the first time period, wherein the difference between the first voltage potential and the second voltage potential is less than the voltage necessary to cause degradation of the antifuse element. Circuitry is provided to sense the voltage on the first conductor at a predetermined time after the start of the third time period and within the first time period. Circuitry is provided to store a signal related to the voltage on the first conductor at the predetermined time after the start of the third time period. Circuitry is provided to communicate the signal to an input/output pad of the integrated circuit.
摘要翻译：用于在由用户形成电子电路之前在集成电路中设置在集成电路中的第一和第二导体之间的反熔丝元件中的欧姆泄漏形式的缺陷测试的装置包括响应于从外部源提供给集成电路的信号的电路用于在第一时间段期间将第一组导体临时连接在一起以形成到第一导体的电路。提供响应于从外部源提供给集成电路的信号的电路，用于将第二组导体临时连接在一起，以在第一时间段内形成到第二导体的电路。提供电路以在第一时间段内的第二时间段内将电荷置于第一导体上，使得选择的动态第一电压电位置于第一导体上。提供电路以在第二时间段之后的第三时间段内并在第一时间段内将第二导体驱动到与所选择的动态第一电压电位不同的第二电压电位，其中第一电压电势与第二电压之间的差电压电位小于导致反熔丝元件劣化所需的电压。提供电路以在第三时间段开始之后的预定时间并且在第一时间段内感测第一导体上的电压。提供电路以在第三时间段开始之后的预定时间存储与第一导体上的电压有关的信号。提供电路以将信号传送到集成电路的输入/输出焊盘。

93. 发明授权

US5198705A Logic module with configurable combinational and sequential blocks 失效
标题翻译：具有可组态组合和顺序块的逻辑模块
公开(公告)号：US5198705A
公开(公告)日：1993-03-30
申请号：US773353
申请日：1991-10-07
申请人： Douglas C. Galbraith , Abbas El Gamal , Jonathan W. Greene
发明人： Douglas C. Galbraith , Abbas El Gamal , Jonathan W. Greene
IPC分类号： H03K3/037 , H03K19/173
CPC分类号： H03K19/1737 , H03K3/037
摘要： A logic module includes first and second multiplexers each having two data inputs and a select input. Both select inputs are connected to the output of a two-input logic gate of a first type. The inputs to the first and second multiplexers comprise data signals from a first group. One input of each logic gate comprises a data signal of a second group and the other input of each logic gate comprises a data signal of a third group. A third multiplexer has first and second data inputs connected the outputs of the first and second multiplexers, respectively, and a select input connected to the output of a two-input logic gate of a second type. Its output is connected to a first data input of a fourth multiplexer having a HOLD1 input coupled to its select input. Its output and a CLEAR input are presented to an AND gate whose output is connected to the second data input of the fourth multiplexer and to the first data input of a fifth multiplexer. The fifth multiplexer select input comprises a HOLD2 input. Its output and the CLEAR input are presented to an AND gate whose output is connected to the second data input of the fifth multiplexer and to an output node. The CLEAR, HOLD1 and HOLD2 inputs comprise combinations of signals from a data signal of a third group which may contain data signals of one of the other groups.
摘要翻译：逻辑模块包括具有两个数据输入和选择输入的第一和第二多路复用器。两个选择输入都连接到第一类型的双输入逻辑门的输出。第一和第二多路复用器的输入包括来自第一组的数据信号。每个逻辑门的一个输入包括第二组的数据信号，并且每个逻辑门的另一个输入包括第三组的数据信号。第三复用器具有分别连接第一和第二多路复用器的输出的第一和第二数据输入以及连接到第二类型的双输入逻辑门的输出的选择输入。其输出连接到具有耦合到其选择输入的HOLD1输入的第四多路复用器的第一数据输入。其输出和CLEAR输入被呈现给AND门，其输出连接到第四多路复用器的第二数据输入端和第五多路复用器的第一数据输入端。第五多路复用器选择输入包括一个HOLD2输入。其输出和CLEAR输入被提供给AND门，其输出连接到第五多路复用器的第二数据输入端和输出节点。 CLEAR，HOLD1和HOLD2输入包括来自第三组的数据信号的信号的组合，其可以包含其他组之一的数据信号。

94. 发明授权

US5132571A Programmable interconnect architecture having interconnects disposed above function modules 失效
标题翻译：具有处于上述功能模块的互连的可编程互连架构
公开(公告)号：US5132571A
公开(公告)日：1992-07-21
申请号：US561110
申请日：1990-08-01
申请人： John L. McCollum , Abbas A. El Gamal , Jonathan W. Greene
发明人： John L. McCollum , Abbas A. El Gamal , Jonathan W. Greene
IPC分类号： H01L21/82 , H01L23/525 , H01L23/528 , H03K19/177
CPC分类号： H01L23/5252 , H01L23/528 , H01L2924/0002
摘要： A user-configurable circuit architecture includes a two dimensional array of functional circuit modules disposed within a semiconductor substrate. A first interconnect layer disposed above and insulated from the semiconductor substrate contains a plurality of conductors and is used for internal connections within the functional circuit modules. A second interconnect layer disposed above and insulated from the first interconnect layer contains a plurality of segmented tracks of conductors running in a first direction and is used to interconnect functional circuit module inputs and outputs. A third interconnect layer disposed above and insulated from the second interconnect layer contains a plurality of segmented tracks of conductors running in a second direction, some of the segments of conductors forming intersections with ones of the segments of the conductors in the second interconnect layer, and is used to interconnect functional circuit module inputs and outputs to implement the desired applications. A plurality of user-configurable interconnect elements are placed directly between the second the third interconnect layers at the intersections of selected segments of the segmented conductors in the second and third interconnect layers. More user-configurable interconnect elements are located between adjacent segments of the segmented conductors in both the second and third interconnect layers. Pass transistors located in the semiconductor substrate in between the functional circuit modules are connected between adjacent segments in both the second and third interconnect layers and between selected intersecting segments in the second and third interconnect layers.

95. 发明授权

US5073729A Segmented routing architecture 失效
标题翻译： SEGMENTED路由架构
公开(公告)号：US5073729A
公开(公告)日：1991-12-17
申请号：US542722
申请日：1990-06-22
申请人： Johathan W. Greene , Abbas A. El Gamal , Sinan Kaptanoglu
发明人： Johathan W. Greene , Abbas A. El Gamal , Sinan Kaptanoglu
IPC分类号： H01L21/82 , G06F17/50 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , G06F17/5077 , H03K19/17704
摘要： A segmented routing architecture includes three or more different interior segment lengths within all of the segmented tracks in a channel. Four or more different segment lengths of interior segments are present in a channel if the sole segment in each unsegmented track is considered, too. Two or more different segment lengths of interior segments exist within a single wiring track. Lengths of adjacent segments within a track are balanced with a ratio not exceeding about two. In any given channel, the average length of all the segments in each column is relatively low in the interior and increases substantially monotonically towards the ends of the channel.

96. 发明授权

US4871933A High-speed static differential sense amplifier 失效
标题翻译：高速静态差分放大器
公开(公告)号：US4871933A
公开(公告)日：1989-10-03
申请号：US239130
申请日：1988-08-31
申请人： Douglas C. Galbraith
发明人： Douglas C. Galbraith
IPC分类号： H03K3/356
CPC分类号： H03K3/356113
摘要： The high-speed static differential sense amplifier of the present invention is composed of two stages. The first stage uses a source follower to feed a set of dual complimentary current mirrors. The current mirrors in the source of the input devices convert the voltage difference supplied by the source follower into a current. This current is mirrored into the second stage by opposing pull-down and pull-up current mirrors from the first stage. The second stage current difference produces the large voltage swings needed to drive the digital logic.
摘要翻译：本发明的高速静态差动读出放大器由两个阶段组成。第一阶段使用源跟随器馈送一组双互补电流镜。输入设备的电源中的电流镜将源极跟随器提供的电压差转换为电流。该电流通过相反的第一级的下拉和上拉电流镜反射到第二级。第二级电流差产生驱动数字逻辑所需的大电压摆幅。

97. 发明授权

US08415650B2 Front to back resistive random access memory cells 有权
标题翻译：从前到后的电阻随机存取存储单元
公开(公告)号：US08415650B2
公开(公告)日：2013-04-09
申请号：US12829311
申请日：2010-07-01
申请人： Jonathan Greene , Frank W. Hawley , John McCollum
发明人： Jonathan Greene , Frank W. Hawley , John McCollum
IPC分类号： H01L29/02
CPC分类号： H03K19/1776 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/149 , H01L45/1616 , H01L45/1625 , H01L45/1675 , H03K19/17724 , Y10S438/90
摘要： A resistive random access memory cell is formed on a semiconductor substrate. First and second diffused regions are disposed in the semiconductor substrate. A polysilicon gate is disposed above the first and second diffused regions. A first contact connects the first diffused region with a region of a first metal layer. A first interlayer dielectric layer is formed over the first metal layer and includes first and second vias, each including conductive plugs connected to the region of the first metal layer. First and second resistive random access memory devices formed over the first interlayer dielectric layer have first and second terminals, and include a dielectric layer and an ion source layer. The first terminals of the first and second resistive random access memory devices are coupled to the first metal layer by the first and second conductive plugs.
摘要翻译：电阻性随机存取存储单元形成在半导体衬底上。第一和第二扩散区域设置在半导体衬底中。多晶硅栅极设置在第一和第二扩散区域上方。第一接触将第一扩散区域与第一金属层的区域连接。第一层间电介质层形成在第一金属层之上，并且包括第一和第二通孔，每个通孔包括连接到第一金属层的区域的导电插塞。形成在第一层间介质层上的第一和第二电阻随机存取存储器件具有第一和第二端子，并且包括电介质层和离子源层。第一和第二电阻随机存取存储器件的第一端子通过第一和第二导电插塞耦合到第一金属层。

98. 发明授权

US08289047B2 Architecture and interconnect scheme for programmable logic circuits 失效
标题翻译：可编程逻辑电路的架构和互连方案
公开(公告)号：US08289047B2
公开(公告)日：2012-10-16
申请号：US12943846
申请日：2010-11-10
申请人： Benjamin S. Ting
发明人： Benjamin S. Ting
IPC分类号： H03K19/177
CPC分类号： H03K19/17704 , H03K19/17728 , H03K19/17736 , H03K19/1778 , H03K19/17796
摘要： An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs).
摘要翻译：用于现场可编程门阵列（FPGA）的分层互连方案架构。

99. 发明授权

US08244791B1 Fast carry lookahead circuits 有权
标题翻译：快速携带查找电路
公开(公告)号：US08244791B1
公开(公告)日：2012-08-14
申请号：US12022721
申请日：2008-01-30
申请人： Volker Hecht , Marcel Derevlean , Jonathan Greene
发明人： Volker Hecht , Marcel Derevlean , Jonathan Greene
IPC分类号： G06F7/50
CPC分类号： G06F7/508
摘要： A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path.
摘要翻译：快速前瞻进位加法器包括耦合到加法器逻辑的加法器逻辑和先行进位逻辑逻辑。进位路径逻辑具有主进位路径，进位入口路径和进位出口路径，进位路径与进位出口路径分离。

100. 发明授权

US08040151B2 Programmable logic device with programmable wakeup pins 有权
标题翻译：具有可编程唤醒引脚的可编程逻辑器件
公开(公告)号：US08040151B2
公开(公告)日：2011-10-18
申请号：US12340440
申请日：2008-12-19
申请人： Theodore Speers
发明人： Theodore Speers
IPC分类号： H03K19/173
CPC分类号： H03K19/17772 , H03K19/17784
摘要： A programmable logic device (PLD) adapted to enter a low-power or sleep mode with programmable wakeup pins in a wakeup group of pins is disclosed. Wake on a single pin change, wake on vector, and wake on a single pin transition are supported. The approach is to select the actively participating pins, enable the desired operation, define the wakeup condition, enter sleep mode, monitor the external signals coupled to the active pins, and exit sleep mode when the wakeup condition is detected.
摘要翻译：公开了一种可编程逻辑器件（PLD），其适于在唤醒组引脚中输入具有可编程唤醒引脚的低功耗或睡眠模式。唤醒单个引脚更改，唤醒向量，并在单引脚转换唤醒被支持。该方法是选择主动参与的引脚，启用所需的操作，定义唤醒条件，进入睡眠模式，监控耦合到活动引脚的外部信号，并在检测到唤醒条件时退出睡眠模式。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式