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    • 1. 发明申请
    • Adaptive decision slicer
    • 自适应决策分片器
    • US20040257253A1
    • 2004-12-23
    • US10464963
    • 2003-06-18
    • Keith R. JonesGilberto Isaac Sada TrevinoWilliam W. Jones
    • H03M003/00H03H007/40
    • G11B20/10203H04L25/03019H04L25/062
    • A method and apparatus is disclosed for adaptively determining threshold values in a decision device, such as a decision slicer. In one embodiment, a slicer receives one or more updated threshold values during operation to adaptively accommodate changes in the received signal or the channel that may occur over time. The updated threshold value is based on a MIN value and a MAX value. The MIN values represent a-value related to a recently received input that was determined to qualify for a particular slicer output and was less than the particular slicer output value. The MAX values represent a value related to a recently received input that was determined to qualify for a particular slicer output and was greater than the particular slicer output value. In one embodiment, the MAX and MIN value computation is based on scaling factors that dampen the rate of change of the threshold value.
    • 公开了用于在决策设备(例如决策限制器)中自适应地确定阈值的方法和装置。 在一个实施例中,限幅器在操作期间接收一个或多个更新的阈值,以自适应地适应随时间发生的接收信号或信道的改变。 更新的阈值基于MIN值和MAX值。 MIN值表示与最近接收的输入相关的值,该输入被确定为符合特定限幅器输出并且小于特定限幅器输出值。 MAX值表示与最近接收到的输入相关的值,该值被确定为限定特定限幅器输出并且大于特定限幅器输出值。 在一个实施例中,MAX和MIN值计算基于削弱阈值变化率的缩放因子。
    • 4. 发明申请
    • RECONFIGURABLE FIR FILTER
    • 可重复FIR滤波器
    • US20040170223A1
    • 2004-09-02
    • US10248920
    • 2003-03-02
    • Tzi-Dar ChiuehKuan-Hung Chen
    • H03K005/159H03H007/30H03H007/40
    • H03H17/0294
    • A series of digit processing units (DPUs) are connected to form a finite impulse response (FIR) filter. Each DPU includes a register, a multiplexer, and a coefficient multiplier. The register stores and delays an input digital signal to be filtered. The multiplexer has inputs connected to the input node and to an output of the register, an output of the multiplexer for connecting to a next stage DPU. The coefficient multiplier is connected to the output of the register and multiplies the input signal by a coefficient or part of a coefficient. A group of DPUs can have multiplexers set so that the register of each DPU stores the same part of the input signal for processing a single filter coefficient. An adder is provided to sum output of the DPUs and output a filtered signal. The critical path of the FIR filter is independent of coefficient number and precision.
    • 一系列数字处理单元(DPU)被连接以形成有限脉冲响应(FIR)滤波器。 每个DPU包括寄存器,多路复用器和系数乘法器。 寄存器存储并延迟要过滤的输入数字信号。 多路复用器具有连接到输入节点和寄存器的输出的输入,多路复用器的输出用于连接到下一级DPU。 系数乘法器连接到寄存器的输出,并将输入信号乘以系数或系数的一部分。 一组DPU可以设置多路复用器,使得每个DPU的寄存器存储用于处理单个滤波器系数的输入信号的相同部分。 提供加法器以对DPU的输出进行求和并输出滤波信号。 FIR滤波器的关键路径与系数数和精度无关。
    • 6. 发明申请
    • Look-ahead decision feedback equalizing receiver
    • 前瞻判决反馈均衡接收机
    • US20040076228A1
    • 2004-04-22
    • US10667658
    • 2003-09-23
    • POSTECH FOUNDATION
    • Hong-June ParkYoung-Soo Sohn
    • H03K005/159H03H007/40H03H007/30
    • H04L25/03878
    • A look-ahead decision feedback equalizing receiver includes an equalizing block for amplifying a high-frequency component of an external data signal fed thereto in response to a predetermined first input signal and a predetermined second input signal, to provide a first equalized external data signal and a second equalized external data signal, respectively; a clock synthesizer for outputting a plurality of sampling clocks, a timing thereof being adjusted by receiving an external clock synchronized with the external data signal; an over-sampler for over-sampling the first equalized external data signal and the second equalized external data signal in synchronization with the sampling clocks; a MUX block for multiplexing the outputs of the over-sampler in response to preceding outputs of the MUX block, which are fed back thereto, to thereby attain MUX decision results; and a phase detector for deciding the timing of the sampling clock by analyzing the MUX decision results.
    • 先行判决反馈均衡接收机包括:用于响应于预定的第一输入信号和预定的第二输入信号放大馈送到其中的外部数据信号的高频分量的均衡块,以提供第一均衡的外部数据信号;以及 第二均衡外部数据信号; 用于输出多个采样时钟的时钟合成器,通过接收与外部数据信号同步的外部时钟来调整定时; 用于与采样时钟同步地对第一均衡外部数据信号和第二均衡外部数据信号进行过采样的过采样器; MUX块,用于响应于所述MUX块的先前输出而多路复用所述过采样器的输出,从而获得MUX判定结果; 以及相位检测器,用于通过分析MUX判定结果来决定采样时钟的定时。