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1. 发明申请

US20040010537A1 Method and apparatus for synthesizing and utilizing waveforms 失效
公开(公告)号：US20040010537A1
公开(公告)日：2004-01-15
申请号：US10617969
申请日：2003-07-10
发明人： Go Tejima , Norihide Yamada
IPC分类号： G06G007/16
CPC分类号： G06G7/26
摘要： A method is provided for synthesizing an arbitrary waveform that approximates a specific waveform. The method includes specifying respective frequencies of component waveforms to be used to generate the arbitrary waveform, the frequencies being less than the maximum frequency needed to synthesize the specific waveform. The method further includes performing a least squares optimization of respective amplitudes and phases of the component waveforms across at least one predetermined time interval. The component waveforms having the amplitudes and phases optimized by the least squares optimization are then summed to produce the arbitrary waveform.

2. 发明申请

US20020070789A1 Field effect transistor square multiplier 有权
标题翻译：场效应晶体管方形乘法器
公开(公告)号：US20020070789A1
公开(公告)日：2002-06-13
申请号：US09829160
申请日：2001-04-09
发明人： Lutz Dathe , Wolfram Kluge
IPC分类号： G06G007/16
CPC分类号： G06G7/20
摘要： A FET square multiplier is disclosed that transforms an input signal into two currents I1 and I2, the difference of which is proportional to the square of the input signal. A first and a second FET are connected at their drains and are source-coupled to the source of a third FET whose transconductance is twice the transconductance of the first and the second FET. The common source node is biased by a constant current source. The FETs are operated in the saturation region to exploit the square dependency of the drain current on the difference of the gate-source voltage and the treshold voltage of an FET.
摘要翻译：公开了一种FET平方乘法器，其将输入信号转换成两个电流I1和I2，其差值与输入信号的平方成比例。第一和第二FET在其漏极处连接并且源极耦合到第三FET的源极，其跨导是第一和第二FET的跨导的两倍。公共源节点被恒定电流源偏置。 FET在饱和区域工作，以利用漏极电流对栅极 - 源极电压和FET的阈值电压差的平方依赖性。

3. 发明申请

US20030110199A1 Multiplier 有权
标题翻译：乘数
公开(公告)号：US20030110199A1
公开(公告)日：2003-06-12
申请号：US10308620
申请日：2002-12-03
发明人： Yoshikatsu Matsugaki , Eizo Fukui
IPC分类号： G06G007/16
CPC分类号： G06G7/163
摘要： A multiplier having a simple constitution, excellent performance with respect to high-frequency characteristics and distortion characteristics, and allows low-voltage operation. Transistor Q11, resistors R11 and R12 form a common-emitter circuit. One signal of differential signal v1 is amplified by the common-emitter circuit, and the amplified signal is input to an emitter follower composed of transistor Q12. The output current of the emitter follower is input through resistor R13 into the current mirror circuit composed of transistors Q13 and Q14. Output current I5 of said current mirror circuit is input to the transistor pair of transistor Q19 and npn transistor Q20. By selecting an appropriate gain for the common-emitter circuit, currents I5 and I6 generated in this way become independent of the base-emitter voltage, and performance is improved with respect to distortion characteristics.
摘要翻译：具有简单结构的乘法器，相对于高频特性和失真特性优异的性能，并且允许低电压操作。晶体管Q11，电阻R11和R12形成共发射极电路。差分信号v1的一个信号由共发射极电路放大，放大的信号被输入到由晶体管Q12组成的射极跟随器。射极跟随器的输出电流通过电阻R13输入到由晶体管Q13和Q14组成的电流镜电路中。所述电流镜电路的输出电流I5被输入到晶体管Q19和npn晶体管Q20的晶体管对。通过为共发射极电路选择合适的增益，以这种方式产生的电流I5和I6与基极 - 发射极电压无关，并且相对于失真特性提高了性能。

4. 发明申请

US20020030529A1 Mixer structure and method for using same 有权
标题翻译：搅拌机结构及使用方法
公开(公告)号：US20020030529A1
公开(公告)日：2002-03-14
申请号：US09985897
申请日：2001-11-06
申请人： GCT Semiconductor, Inc.
发明人： Kyeongho Lee , Deog-Kyoon Jeong
IPC分类号： G06G007/16
CPC分类号： H04B1/40 , H03D7/1441 , H03F2200/372 , H03H11/22 , H03H2011/0494 , H03K9/00 , H03L7/0891 , H03L7/0995 , H03L7/1974 , H04B1/28 , H04B1/403
摘要： A mixer structure and method for using same in accordance with the present invention includes a multi-phase mixer. A VCO includes a plurality of differential delay cells to output a plurality of multi-phase clock signals. The multi-phase mixer can include a load circuit, switch circuit, noise reduction circuit and an input circuit. The switch circuit is coupled to receive the plurality of multi-phase clock signals and includes a first switch array and a second switch array coupled to the load circuit, respectively. The noise reduction circuit coupled to the switch circuit can include a transistor responsive to a bias voltage. The input circuit includes a transistor receiving the input signal. The first switch array includes a first plurality of switches coupled between a first output terminal and a second node, and the second switch array includes a second plurality of switches coupled between a second output terminal and the second node. Preferably, each of the plurality of switches includes two pairs of serially connected transistors, wherein the serially connected transistors are coupled in parallel to provide a symmetric electrical connection for each of two input ports. The mixer and method for using same can be single or double-balanced mixers receiving an RF input signal.
摘要翻译：根据本发明的混合器结构及其使用方法包括多相混合器。 VCO包括多个差分延迟单元，以输出多个多相时钟信号。多相混频器可以包括负载电路，开关电路，降噪电路和输入电路。开关电路被耦合以接收多个多相时钟信号，并且包括分别耦合到负载电路的第一开关阵列和第二开关阵列。耦合到开关电路的降噪电路可以包括响应偏置电压的晶体管。输入电路包括接收输入信号的晶体管。第一开关阵列包括耦合在第一输出端子和第二节点之间的第一多个开关，并且第二开关阵列包括耦合在第二输出端子和第二节点之间的第二多个开关。优选地，多个开关中的每一个包括两对串联连接的晶体管，其中串联连接的晶体管并联耦合以为两个输入端口中的每一个提供对称电连接。混频器和使用它的方法可以是接收RF输入信号的单或双平衡混频器。

5. 发明申请

US20010048335A1 Frequenecy multiplier circuit and method using above circuit for a period time division in subperiods, for a brushless motor 有权
标题翻译：频率乘法器电路和方法使用上述电路在子周期内进行时段分时，用于无刷电机
公开(公告)号：US20010048335A1
公开(公告)日：2001-12-06
申请号：US09872632
申请日：2001-06-01
发明人： Roberto Bardelli
IPC分类号： G06G007/16
CPC分类号： G06F7/68
摘要： The present invention relates a frequency multiplier circuit and a controlling method thereof, characterised in that it measures a period of a waveform by a fixed frequency timing signal, and that it reproduces said period by approaching a number of prefixed length subperiods as equal as possible to each other so to minimise the reproduction error thanks to the interpretation of said subperiod number in the following manner mnullj * 2null.
摘要翻译：本发明涉及一种倍频电路及其控制方法，其特征在于，其通过固定频率定时信号测量波形的周期，并且通过接近多个前缀长度子周期来再现所述周期，所述预定长度子周期等于由于以下述方式对所述次周期数进行解释，所以为了最小化再现误差，m = j * 2'。

6. 发明申请

US20010040477A1 Circuit configuration for mixing an input signal and an oscillator signal with one another 失效
标题翻译：用于将输入信号和振荡器信号彼此混合的电路配置
公开(公告)号：US20010040477A1
公开(公告)日：2001-11-15
申请号：US09822017
申请日：2001-03-30
发明人： Stephane Catala
IPC分类号： G06G007/16
CPC分类号： H03D7/1433 , H03D7/1425 , H03D7/1491 , H03D7/165
摘要： The circuit configuration mixes an input signal with an oscillator signal. A phase splitter with one input and two voltage outputs receives the oscillator signal and carries at its outputs orthogonal oscillator signals, which are phase-shifted through 90null with respect to one another. A first differential amplifier has a voltage input connected to one of the two voltage outputs of the phase splitter. A second differential amplifier has a voltage input connected to the other of the two voltage outputs of the phase splitter and one current output. A first current source controlled by the input signal supplies the first differential amplifier. A second current source that is controlled by the input signal supplies the second differential amplifier. A first phase shifter is connected downstream of the first differential amplifier, and a second phase shifter is connected downstream of the second differential amplifier. An adder device is connected downstream from the first and second differential amplifiers and produces an output signal.
摘要翻译：电路配置将输入信号与振荡器信号进行混合。具有一个输入和两个电压输出的分相器接收振荡器信号并在其输出端承载正交振荡器信号，它们相对于彼此相移90°。第一差分放大器具有连接到相分离器的两个电压输出之一的电压输入。第二差分放大器具有连接到分相器的两个电压输出中的另一个的电压输入和一个电流输出。由输入信号控制的第一电流源提供第一差分放大器。由输入信号控制的第二电流源提供第二差分放大器。第一移相器连接在第一差分放大器的下游，第二移相器连接在第二差分放大器的下游。加法器装置连接在第一和第二差分放大器的下游，并产生输出信号。

7. 发明申请

US20040210618A1 Galois field linear transformer trellis system 失效
标题翻译：伽罗瓦斯线性变压器网格系统
公开(公告)号：US20040210618A1
公开(公告)日：2004-10-21
申请号：US10753301
申请日：2004-01-07
发明人： Yosef Stein , Haim Primo
IPC分类号： G06G007/16
CPC分类号： H03M13/235 , H03M13/6516 , H03M13/6561 , H03M13/6575 , H04L1/0041 , H04L1/0059
摘要： A Galois field linear transformer trellis system includes a Galois field linear transformer matrix; an input selection circuit for providing to the matrix a number of input bits in one or more trellis bit streams and a trellis state output of the matrix and a programmable storage device for configuring the matrix to perform a multi-cycle Galois field transform of the one or more trellis bit steams and trellis state output to provide a plurality of trellis output channel symbols and a new trellis state output in a single cycle.
摘要翻译：伽罗瓦域线性变压器网格系统包括伽罗瓦域线性变压器矩阵; 输入选择电路，用于向矩阵提供一个或多个格状比特流中的多个输入比特和该矩阵的网格状态输出，以及用于配置该矩阵以执行该一矩阵的多周期伽罗瓦域变换的可编程存储装置或更多的网格位流和网格状态输出，以在单个周期中提供多个网格输出通道符号和新的网格状态输出。

8. 发明申请

US20040174202A1 High linearity passive mixer and associated LO buffer 失效
标题翻译：高线性无源混频器和相关LO缓冲器
公开(公告)号：US20040174202A1
公开(公告)日：2004-09-09
申请号：US10382811
申请日：2003-03-06
发明人： Arya Reza Behzad
IPC分类号： G06G007/16
CPC分类号： H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D2200/0033 , H03D2200/0043 , H03D2200/0088
摘要： An RF communications system includes a transmit node for transmitting an RF information signal and a receive node for receiving the transmitted RF information signal. The receive node includes a passive mixer coupled to an amplifier for producing an IF or baseband differential mixer output signal as a function of a LO drive signal. The passive mixer having a first plurality of transistors of a first polarity type arranged in a ring configuration and a second plurality of transistors of a second polarity type, wherein each of second plurality of transistors is coupled to one of said first plurality of transistors.
摘要翻译： RF通信系统包括用于发送RF信息信号的发送节点和用于接收发送的RF信息信号的接收节点。接收节点包括耦合到放大器的无源混频器，用于产生作为LO驱动信号的函数的IF或基带差分混频器输出信号。无源混频器具有以环形配置的第一极性类型的第一多个晶体管和第二极性类型的第二多个晶体管，其中第二多个晶体管中的每一个耦合到所述第一多个晶体管中的一个。

9. 发明申请

US20030169090A1 Mixer with exponentially variable gain 有权
标题翻译：具有指数可变增益的混频器
公开(公告)号：US20030169090A1
公开(公告)日：2003-09-11
申请号：US10352788
申请日：2003-01-28
申请人： STMicroelectronics S.r.l.
发明人： Pietro Filoramo , Angelo Granata
IPC分类号： G06G007/20 , G06G007/16 , G06F007/44
CPC分类号： H03G1/0023 , H03D7/1433 , H03D7/1458 , H03D7/1491 , H03D2200/0025 , H03D2200/0043
摘要： An exponentially variable gain mixer circuit includes an oscillating circuit generating an alternating differential signal. A correction circuit is connected to the oscillating circuit and includes a first amplifier and a differential amplifier. The first amplifier receives an external gain variation command and generates a differential output signal that includes a control voltage and a bias voltage. The differential amplifier receives the alternating differential signal and generates a differential modulation signal. A variable gain mixer receives an input differential signal and generates an amplified differential signal as a function of the differential modulation signal and the control voltage.
摘要翻译：指数可变增益混频器电路包括产生交流差分信号的振荡电路。校正电路连接到振荡电路，并包括第一放大器和差分放大器。第一放大器接收外部增益变化指令，并产生包括控制电压和偏置电压的差分输出信号。差分放大器接收交流差分信号并产生差分调制信号。可变增益混频器接收输入差分信号并产生作为差分调制信号和控制电压的函数的放大的差分信号。

10. 发明申请

US20030071675A1 Circuit and method to facilitate threshold voltage extraction and facilitate operation of a capacitor multiplier 有权
标题翻译：电路和方法，便于阈值电压提取，便于电容乘法器的运算
公开(公告)号：US20030071675A1
公开(公告)日：2003-04-17
申请号：US09977609
申请日：2001-10-15
发明人： Richard Kane Stair , Gabriel A. Rincon-Mora
IPC分类号： G06G007/16
CPC分类号： G06G7/625
摘要： A system and method to extract a threshold voltage for a MOSFET are disclosed. First and second stages, which include inputs that receive functionally related input currents, are connected to each other. The first stage includes a second input that is coupled to a corresponding input of the second stage through part of a voltage divider. Another part of the voltage divider is coupled between an internal gate node and the input of the second stage that receives the respective input current. The input of the second stage that receives the respective input current also provides an output voltage substantially equal to the threshold voltage for one or both of the MOSFETs.
摘要翻译：公开了提取MOSFET的阈值电压的系统和方法。包括接收功能相关输入电流的输入的第一和第二级彼此连接。第一级包括通过分压器的一部分耦合到第二级的相应输入的第二输入。分压器的另一部分耦合在内部栅极节点和接收相应输入电流的第二级的输入之间。接收相应输入电流的第二级的输入还提供基本上等于一个或两个MOSFET的阈值电压的输出电压。

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