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1. 发明授权

US09015551B2 Decoding apparatus with de-interleaving efforts distributed to different decoding phases and related decoding method thereof 有权
标题翻译：具有解交织功能的解码装置分配到不同的解码阶段及其相关的解码方法
公开(公告)号：US09015551B2
公开(公告)日：2015-04-21
申请号：US13798112
申请日：2013-03-13
申请人： MediaTek Inc.
发明人： Wei-De Wu , Chiaming Lo
IPC分类号： H03M13/00 , H03M13/27 , H03M13/29 , H03M13/39
CPC分类号： H03M13/2778 , H03M13/271 , H03M13/2714 , H03M13/2775 , H03M13/2957 , H03M13/3905 , H03M13/3972
摘要： A decoding apparatus includes a memory device and a decoding circuit. The memory device is arranged for storing a data block with inter-row interleaving in a plurality of data rows of the data block and without intra-row interleaving in each of the data rows. The decoding circuit is coupled to the memory device. The decoding circuit is arranged for accessing the memory device to perform a first decoding operation with inter-row de-interleaving memory access, and accessing the memory device to perform a second decoding operation with intra-row de-interleaving memory access.
摘要翻译：解码装置包括存储装置和解码电路。存储器件被布置为在数据块的多个数据行中存储具有行间交错的数据块，并且在每个数据行中不存在行内交织。解码电路耦合到存储器件。解码电路被布置为访问存储器件以执行具有行间解交织存储器访问的第一解码操作，并且访问存储器件以执行具有行内解交织存储器访问的第二解码操作。

2. 发明申请

US20140068117A1 METHOD AND APPARATUS FOR TURBO DECODER MEMORY COLLISION RESOLUTION 有权
标题翻译： TURBO解码器存储器碰撞分辨率的方法和装置
公开(公告)号：US20140068117A1
公开(公告)日：2014-03-06
申请号：US13599926
申请日：2012-08-30
申请人： Axel Huebner , Jens Berkmann , Michael Janning
发明人： Axel Huebner , Jens Berkmann , Michael Janning
IPC分类号： G06F3/00
CPC分类号： G06F13/16 , G06F13/1673 , G06F13/376 , G06F13/38 , H03M13/2775 , H03M13/2957
摘要： A device such as a turbo decoding device is proposed in which an intermediate buffering device including an address buffering device and an element buffering device is communicatively coupled to a plurality of processing devices and a memory device. During a cycle of a parallel decoding process, the intermediate buffering device receives, from two different processing devices, first and second address information respectively corresponding to first and second elements of a code sequence stored in the memory device. During the cycle, the intermediate buffering device transmits a request for the first element to the memory device based on the first address information and stores the second address information in the address buffering device. Subsequently, during the cycle, the intermediate buffering device receives first element information corresponding to the first element from the memory device and stores the received first element information in the element buffering device.
摘要翻译：提出了诸如turbo解码装置的装置，其中包括地址缓冲装置和元素缓冲装置的中间缓冲装置通信地耦合到多个处理装置和存储装置。在并行解码处理的周期期间，中间缓冲装置从两个不同的处理装置接收分别对应于存储在存储装置中的代码序列的第一和第二元素的第一和第二地址信息。在该循环期间，中间缓冲装置基于第一地址信息向存储装置发送对第一元素的请求，并将第二地址信息存储在地址缓冲装置中。随后，在该周期期间，中间缓冲装置从存储装置接收对应于第一元素的第一元素信息，并将接收到的第一元素信息存储在元素缓存装置中。

3. 发明授权

US08572456B1 Avoiding interleaver memory conflicts 有权
标题翻译：避免交织器内存冲突
公开(公告)号：US08572456B1
公开(公告)日：2013-10-29
申请号：US12470959
申请日：2009-05-22
申请人： Zhengjun Pan , Volker Mauer
发明人： Zhengjun Pan , Volker Mauer
IPC分类号： H03M13/00
CPC分类号： H03M13/2775
摘要： Interleaving and deinterleaving schemes for operating in parallel on sections of a data block to load memories with respective segments of a reordered version of the block, in a manner which can avoid memory conflicts.
摘要翻译：在数据块的各个部分上并行操作的交错和解交织方案，以能够避免存储器冲突的方式加载具有块的重新排版版本的各个段的存储器。

4. 发明申请

US20130198592A1 TURBO CODE PARALLEL INTERLEAVER AND PARALLEL INTERLEAVING METHOD THEREOF 有权
标题翻译：涡轮代码并行交互和并行交互方法
公开(公告)号：US20130198592A1
公开(公告)日：2013-08-01
申请号：US13825886
申请日：2011-03-25
申请人： Yi Wang
发明人： Yi Wang
IPC分类号： H03M13/29
CPC分类号： H03M13/2903 , H03M13/271 , H03M13/2739 , H03M13/2764 , H03M13/2775 , H03M13/2782 , H03M13/2957 , H03M13/3972
摘要： A Turbo code parallel interleaver and a parallel interleaving method are disclosed by the disclosure. The Turbo code parallel interleaver comprises: an interleaving unit, configured to generate a column address for parallel-reading data and a row address of each row of data being row-interleaved, input the column address and the column address after delay to a CB matrix unit, input the row address of each row to a switching output unit, and input the row address of each row after delay to a switching input unit; a switching output unit, configured to receive the data of each row output by the CB matrix unit, perform the inter-row interleaving for the data of each row according to the row address of each row, and input the interleaved data to a parallel MAP unit for the MAP computing; and a switching input unit.
摘要翻译：本公开公开了Turbo码并行交织器和并行交错方法。 Turbo码并行交织器包括：交织单元，被配置为产生用于并行读取数据的列地址和被行交错的每行数据的行地址，将延迟后的列地址和列地址输入到CB矩阵将每行的行地址输入到切换输出单元，并将延迟后的每行的行地址输入到切换输入单元; 开关输出单元，被配置为接收由CB矩阵单元输出的每一行的数据，根据每行的行地址对每行的数据执行行间交织，并将交织的数据输入到并行MAP MAP计算单位; 和切换输入单元。

5. 发明授权

US08291291B1 Data resequencing 有权
标题翻译：数据重新排序
公开(公告)号：US08291291B1
公开(公告)日：2012-10-16
申请号：US12291695
申请日：2008-11-13
申请人： Zhengjun Pan , Suleyman Sirri Demirsoy , Volker Mauer , Kellie Marks
发明人： Zhengjun Pan , Suleyman Sirri Demirsoy , Volker Mauer , Kellie Marks
IPC分类号： G06F11/00
CPC分类号： H03M13/2739 , H03M13/2764 , H03M13/2775 , H03M13/6525 , H03M13/6561 , H04L1/0071
摘要： Interleaving in which functions relating final and original positions are implemented with low complexity using inequalities based on the functions.
摘要翻译：使用基于功能的不等式，以最低复杂度实现关于最终和原始职位的功能的交织。

6. 发明授权

US08200733B1 Device having interleaving capabilities and a method for applying an interleaving function 有权
标题翻译：具有交织能力的装置和应用交织功能的方法
公开(公告)号：US08200733B1
公开(公告)日：2012-06-12
申请号：US12102996
申请日：2008-04-15
申请人： Yuval Neeman , Ron Berkovich , Guy Drory , Gilad Dror , Aviel Livay , Yonatan Naor
发明人： Yuval Neeman , Ron Berkovich , Guy Drory , Gilad Dror , Aviel Livay , Yonatan Naor
IPC分类号： G06F7/38
CPC分类号： H04L1/0071 , H03M13/2739 , H03M13/2775 , H03M13/2957 , H03M13/3972 , H03M13/6525
摘要： A method and a device having interleaving capabilities, the device comprises a first interleaver; the first interleaver comprises a first register, a second register, a first adder and a second adder; wherein the first register is coupled to the first adder and to the second adder; wherein the second register is coupled to the second adder; wherein the first adder is adapted to add a current first register value to a first coefficient to provide a next first register value that is stored at the first register; wherein the second adder is adapted to add a current first register value to a second coefficient, to a third coefficient and to a current second register value to provide an interleaved output value.
摘要翻译：一种具有交织能力的方法和装置，所述装置包括第一交织器; 第一交织器包括第一寄存器，第二寄存器，第一加法器和第二加法器; 其中所述第一寄存器耦合到所述第一加法器和所述第二加法器; 其中所述第二寄存器耦合到所述第二加法器; 其中所述第一加法器适于将当前第一寄存器值添加到第一系数以提供存储在所述第一寄存器的下一个第一寄存器值; 其中所述第二加法器适于将当前第一寄存器值添加到第二系数到第三系数和当前第二寄存器值以提供交错输出值。

7. 发明申请

US20120102381A1 SIMPLIFIED PARALLEL ADDRESS-GENERATION FOR INTERLEAVER 有权
标题翻译：简化的并行地址生成
公开(公告)号：US20120102381A1
公开(公告)日：2012-04-26
申请号：US12912147
申请日：2010-10-26
申请人： Shai Kalfon , Moshe Bukris
发明人： Shai Kalfon , Moshe Bukris
IPC分类号： H03M13/07 , G06F11/10
CPC分类号： H03M13/276 , H03M13/2739 , H03M13/2775
摘要： An apparatus including a first circuit and a second circuit. The first circuit may be configured to store a block of data values arranged in a first order. The first circuit may be further configured to present a plurality of the data values in parallel in response to a plurality of address signals, where the data values are presented in a second order. The second circuit may be configured to generate the plurality of address signals in response to a first signal, a second signal and a third signal. The second circuit generally includes an even number of address generators configured to generate the plurality of address signals in parallel.
摘要翻译：一种包括第一电路和第二电路的装置。第一电路可以被配置为存储以一级排列的数据值块。第一电路可以被进一步配置为响应于多个地址信号并行地呈现多个数据值，其中数据值以二次呈现。第二电路可以被配置为响应于第一信号，第二信号和第三信号而产生多个地址信号。第二电路通常包括偶数个地址发生器，其被配置为并行地生成多个地址信号。

8. 发明授权

US08051239B2 Multiple access for parallel turbo decoder 有权
标题翻译：并行turbo解码器的多路访问
公开(公告)号：US08051239B2
公开(公告)日：2011-11-01
申请号：US11810199
申请日：2007-06-04
申请人： Esko Nieminen
发明人： Esko Nieminen
IPC分类号： G06F12/00
CPC分类号： H03M13/29 , G06F9/345 , G06F9/3885 , H03M13/276 , H03M13/2771 , H03M13/2775 , H03M13/2957 , H03M13/6525 , H03M13/653 , H03M13/6544 , H03M13/6558 , H03M13/6561 , H03M13/6566 , H04L1/0071
摘要： A memory bank contains a plurality of memories, a first Butterfly network is configured to apply memory addresses to the memory bank, and a second Butterfly network is configured to pass data to or from the memory bank. A control signal is generated for the first and second Butterfly networks in accordance with a multiple access rule to enable parallel access to the memory bank, without memory access conflict, for one of a linear order and an interleaved order. The method and apparatus is particularly advantageous for use in turbo decoding.
摘要翻译：存储体包含多个存储器，第一Butterfly网络被配置为将存储器地址应用于存储体，并且第二Butterfly网络被配置为将数据传送到存储体或从存储体传递数据。根据多址规则为第一和第二蝴蝶网络生成控制信号，以使得能够以线性顺序和交错顺序之一并行访问存储体而无需存储器访问冲突。该方法和装置特别有利于用于turbo解码。

9. 发明授权

US07975203B2 Quadratic polynomial permutation (QPP) interleaver providing hardware savings and flexible granularity adaptable to any possible turbo code block size 有权
标题翻译：二次多项式置换（QPP）交织器，提供硬件节省和灵活的粒度，适用于任何可能的turbo码块大小
公开(公告)号：US07975203B2
公开(公告)日：2011-07-05
申请号：US11810890
申请日：2007-06-07
申请人： Ba-Zhong Shen , Tak K. Lee
发明人： Ba-Zhong Shen , Tak K. Lee
IPC分类号： H03M13/00
CPC分类号： H03M13/2957 , H03M13/2757 , H03M13/2775 , H03M13/3972 , H03M13/6356 , H03M13/6362 , H03M13/6508 , H03M13/6525 , H03M13/6566
摘要： Quadratic polynomial permutation (QPP) interleaver providing hardware saving and flexible granularity adaptable to any possible turbo code block size. A means is presented by which only a very small number of coefficients need be stored to effectuate a wide variety of QPP interleaves as can be employed in the context of turbo coding. In one instance, to accommodate the approximate 6000 different turbo code block sizes in 3GPP LTE channel coding, only 5 different coefficient values need to be stored to effectuate a very broad range of QPP interleaves to be applied each of those various turbo code block sizes. Moreover, a few small number of dummy bits, if any, need to be employed to accommodate a very broad range of turbo code block sizes. It is noted that the QPP interleaving as described herein can be applied to turbo encoding and turbo decoding (e.g., including both interleaving and de-interleaving).
摘要翻译：二次多项式置换（QPP）交织器，提供适用于任何可能的turbo码块大小的硬件保存和灵活的粒度。提出了一种手段，其中仅需要非常少量的系数来存储多个QPP交织以便在turbo编码的上下文中使用。在一种情况下，为了适应3GPP LTE信道编码中的大约6000个不同的Turbo码块大小，仅需要存储5个不同的系数值，以实现要应用那些各种turbo码块大小中的每一个的非常宽范围的QPP交织。此外，需要采用少量的虚拟位（如果有的话）以适应非常宽范围的turbo码块大小。注意，如本文所述的QPP交织可以应用于turbo编码和turbo解码（例如，包括交织和解交织两者）。

10. 发明授权

US07827473B2 Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors 失效
标题翻译： Turbo解码器采用ARP（几乎规则排列）交错和任意数量的解码处理器
公开(公告)号：US07827473B2
公开(公告)日：2010-11-02
申请号：US11811014
申请日：2007-06-07
申请人： Tak K. Lee , Ba-Zhong Shen
发明人： Tak K. Lee , Ba-Zhong Shen
IPC分类号： H03M13/03
CPC分类号： G06F11/1008 , H03M13/2753 , H03M13/2775 , H03M13/2957 , H03M13/3905 , H03M13/3972
摘要： Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors. A novel approach is presented herein by which an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) be employed to perform decoding of a turbo coded signal while still using a selected embodiment of an ARP (almost regular permutation) interleave. The desired number of decoding processors is selected, and very slight modification of an information block (thereby generating a virtual information block) is made to accommodate that virtual information block across all of the decoding processors during all decoding cycles except some dummy decoding cycles. In addition, contention-free memory mapping is provided between the decoding processors (e.g., a plurality of turbo decoders) and memory banks (e.g., a plurality of memories).
摘要翻译： Turbo解码器采用ARP（几乎规则排列）交错和任意数量的解码处理器。本文提出了一种新颖的方法，通过该方法，使用任意选择的数量（M）的解码处理器（例如，多个并行实现的turbo解码器）来执行turbo编码信号的解码，同时仍然使用所选择的ARP实施例（几乎正则排列）交错。选择所需数量的解码处理器，并且进行信息块（从而生成虚拟信息块）的非常轻微的修改以在除了一些虚拟解码周期之外的所有解码周期期间在所有解码处理器之间容纳该虚拟信息块。此外，在解码处理器（例如，多个turbo解码器）和存储体（例如，多个存储器）之间提供无竞争的存储器映射。

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