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1. 发明公开

US20230318580A1 SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
公开(公告)号：US20230318580A1
公开(公告)日：2023-10-05
申请号：US18328335
申请日：2023-06-02
申请人： SEIKO EPSON CORPORATION
发明人： Yoshiyuki Yamaguchi
IPC分类号： H03K3/011 , H03K3/36 , H03K3/0231 , H03L1/04 , H03L1/02
CPC分类号： H03K3/011 , H03K3/36 , H03K3/0231 , H03L1/04 , H03L1/026
摘要： Provided is a semiconductor integrated circuit including an oscillation circuit configured to output an oscillation signal, a heater configured to heat the oscillation circuit, a temperature sensor configured to detect a temperature of the oscillation circuit, and a nonvolatile memory configured to store temperature correction data. The oscillation circuit controls a frequency of the oscillation signal based on an output signal of the temperature sensor and the temperature correction data.

2. 发明授权

US09912320B2 Exponentially scaling switched capacitor 有权
公开(公告)号：US09912320B2
公开(公告)日：2018-03-06
申请号：US15180442
申请日：2016-06-13
申请人： The Hong Kong University of Science and Technology
发明人： Howard Cam Luong , Zhiqiang Huang
IPC分类号： H03J3/18 , H03B5/12 , H03H7/00 , H03K3/36
CPC分类号： H03J3/185 , H03H7/004 , H03H7/24 , H03K3/36 , H03L7/0991 , H03L2207/50
摘要： An exponentially-scaling switched impedance circuit includes: two or more impedance scaling circuits, wherein each impedance scaling circuit comprises: an input port; an output port; and a switched impedance circuit connected in parallel to the output port. Each impedance scaling circuit is configured to provide an effective impedance at the input port corresponding to a scaled-down version of the exponentially-scaling switched impedance circuit. The two or more impedance scaling circuits are connected in a cascade such that an input of an impedance scaling circuit is connected to an output of a previous impedance scaling circuit and/or an output of the impedance scaling circuit is connected to an input of a next impedance scaling circuit.

3. 发明申请

US20180061741A1 SEMICONDUCTOR DIE PACKAGE AND METHOD OF PRODUCING THE PACKAGE 有权
公开(公告)号：US20180061741A1
公开(公告)日：2018-03-01
申请号：US15686015
申请日：2017-08-24
申请人： IMEC VZW
发明人： Eric Beyne
IPC分类号： H01L23/48 , H01L27/105 , H03K3/36
CPC分类号： H01L23/481 , H01L21/561 , H01L21/568 , H01L23/3135 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/96 , H01L24/97 , H01L27/1052 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/16235 , H01L2224/32145 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/73209 , H01L2224/73253 , H01L2224/73267 , H01L2224/81005 , H01L2224/81815 , H01L2224/83005 , H01L2224/92124 , H01L2224/97 , H01L2924/1431 , H01L2924/1434 , H01L2924/1436 , H01L2924/15192 , H01L2924/15311 , H03K3/36 , H01L2224/81 , H01L2224/83
摘要： A package including a first die embedded in a reconstructed wafer obtainable by the known FO-WLP or eWLB technologies is disclosed. In one aspect and in addition to the first die, a Through Substrate Via insert is embedded in the wafer, the TSV insert being a separate element, possibly a silicon die with metal filled vias interconnecting contacts on the front and back sides of the insert. A second die is mounted on the back side of the substrate, with contacts on the second die in electrical connection with the TSV insert's contacts on the back side of the substrate. On the front side of the substrate, a lateral connecting device is mounted which interconnects the TSV insert's contacts on the front side of the substrate to contacts on the front side of the first die. The lateral connecting device and the TSV insert thereby effectively interconnect the contacts on the first and second dies. In another aspect, the lateral connecting device is mounted on a redistribution layer on the front side of the substrate, as it is known from FO-WLP technology.

4. 发明授权

US09831878B2 Semiconductor device and selector circuit 有权
公开(公告)号：US09831878B2
公开(公告)日：2017-11-28
申请号：US15291677
申请日：2016-10-12
申请人： LAPIS Semiconductor Co., Ltd.
发明人： Shigeru Nagatomo
IPC分类号： H03K19/0185 , H01L27/092 , H03K3/36 , H03K3/356 , H03K17/22 , H01L29/06
CPC分类号： H03K19/018521 , H01L27/092 , H01L29/0684 , H03K3/356113 , H03K3/356165 , H03K3/36 , H03K17/223
摘要： A semiconductor device includes a setting circuit and a reset circuit. The setting circuit includes a latch circuit having first and second inverters driven by a first power voltage whose level is fixed and a first transistor which is switched between an ON state and an OFF state on the basis of a level of a second power voltage whose level varies depending on a surrounding environment, and sets data corresponding to a reference voltage to the latch circuit in response to the first transistor being switched to the ON state. The reset circuit includes an N-type second transistor connected to an output of the first inverter and an input of the second inverter. The second transistor sets data corresponding to the reference voltage to the latch circuit in response to the second voltage being equal to or lower than a predetermined voltage value.

5. 发明申请

US20140374760A1 PULSE OUTPUT CIRCUIT, SHIFT REGISTER, AND DISPLAY DEVICE 有权
标题翻译：脉冲输出电路，移位寄存器和显示设备
公开(公告)号：US20140374760A1
公开(公告)日：2014-12-25
申请号：US14318809
申请日：2014-06-30
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Hiroyuki Miyake
IPC分类号： H01L27/12
CPC分类号： H01L27/1251 , G09G2310/0267 , G09G2310/0275 , G11C19/00 , G11C19/184 , H01L27/1222 , H01L27/124 , H03K3/36
摘要： An object is to suppress change of a threshold voltage of a transistor in a shift register and to prevent the transistor from malfunctioning during a non-selection period. A pulse output circuit provided in the shift register regularly supplies a potential to a gate electrode of a transistor which is in a floating state so that the gate electrode is turned on during a non-selection period when a pulse is not outputted. In addition, supply of a potential to the gate electrode of the transistor is performed by turning on or off another transistor regularly.
摘要翻译：目的是抑制移位寄存器中的晶体管的阈值电压的变化，并且防止晶体管在非选择期间发生故障。设置在移位寄存器中的脉冲输出电路有规律地向处于浮置状态的晶体管的栅电极提供电位，使得在不输出脉冲的非选择期间，栅电极导通。此外，通过定期导通或关闭另一个晶体管来提供晶体管的栅电极的电位。

6. 发明申请

US20140232480A1 CLOCK APPARATUS 审中-公开
标题翻译：时钟设备
公开(公告)号：US20140232480A1
公开(公告)日：2014-08-21
申请号：US13769829
申请日：2013-02-19
申请人： ISSC TECHNOLOGIES CORP.
发明人： Yi-Lung Chen
IPC分类号： H03K3/36
CPC分类号： H03K3/36 , H03K3/03
摘要： The invention provides a clock apparatus includes a clock source, a first resistor, a diode, an amplifier, and an oscillator. The current source provides a current, and the current has a first temperature coefficient. The first resistor has a first end, and the first end receives the current. The anode of the diode is coupled to a second end of the first resistor, the cathode of the diode is coupled to a reference ground. The diode has a second temperature coefficient. The amplifier receives a power source. The amplifier generates an output voltage according to the power source and a voltage on the first end of the first resistor. The oscillator receives the output voltage to be an operating power. Wherein, the first and second temperature coefficients are complementary.
摘要翻译：本发明提供一种时钟装置，包括时钟源，第一电阻器，二极管，放大器和振荡器。电流源提供电流，电流具有第一温度系数。第一电阻具有第一端，第一端接收电流。二极管的阳极耦合到第一电阻器的第二端，二极管的阴极耦合到参考地。二极管具有第二温度系数。放大器接收电源。放大器根据电源产生输出电压，并在第一电阻的第一端产生电压。振荡器接收输出电压为工作电源。其中，第一和第二温度系数是互补的。

7. 发明授权

US08766901B2 Pulse output circuit, shift register, and display device 有权
标题翻译：脉冲输出电路，移位寄存器和显示器件
公开(公告)号：US08766901B2
公开(公告)日：2014-07-01
申请号：US13949371
申请日：2013-07-24
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Hiroyuki Miyake
IPC分类号： G09G3/36
CPC分类号： H01L27/1251 , G09G2310/0267 , G09G2310/0275 , G11C19/00 , G11C19/184 , H01L27/1222 , H01L27/124 , H03K3/36
摘要： An object is to suppress change of a threshold voltage of a transistor in a shift register and to prevent the transistor from malfunctioning during a non-selection period. A pulse output circuit provided in the shift register regularly supplies a potential to a gate electrode of a transistor which is in a floating state so that the gate electrode is turned on during a non-selection period when a pulse is not outputted. In addition, supply of a potential to the gate electrode of the transistor is performed by turning on or off another transistor regularly.
摘要翻译：目的是抑制移位寄存器中的晶体管的阈值电压的变化，并且防止晶体管在非选择期间发生故障。设置在移位寄存器中的脉冲输出电路有规律地向处于浮置状态的晶体管的栅电极提供电位，使得在不输出脉冲的非选择期间，栅电极导通。此外，通过定期导通或关闭另一个晶体管来提供晶体管的栅电极的电位。

8. 发明授权

US5438284A Basic logic circuit having multi-emitter transistor 失效
标题翻译：具有多发射极晶体管的基本逻辑电路
公开(公告)号：US5438284A
公开(公告)日：1995-08-01
申请号：US317738
申请日：1994-10-04
申请人： Motomu Takatsu
发明人： Motomu Takatsu
IPC分类号： H01L29/68 , H01L29/205 , H03K3/037 , H03K3/36 , H03K19/08 , H03K19/082 , H03K19/20
CPC分类号： H03K3/36 , H03K19/082 , H03K3/037
摘要： A basic logic circuit 10 which functions as a data selector consists of a basic circuit 11, a HET (hot electron transistor) 12, the first and second emitters of which are connected to the first emitter of a HET 16 and a data input end A respectively, and an inverter 13 connected to an output end of the circuit 11. In a HET 14 having no base electrode, its collector is connected to a power supply line VCC via a load resistor 15, its first emitter is used exclusively for current output by connecting to the collector of the HET 16 the second emitter of which is connected to a power supply line VSS, its second emitter is used for current input/output by directly connected to a control input end S, and its third emitter is used exclusively for current input by connecting to the first emitter of a HET 17 the second emitter of which is connected to a data input end B. An output data Q is equal to an input data A/B when a control data S is high/low level respectively.
摘要翻译：用作数据选择器的基本逻辑电路10包括基本电路11，HET（热电子晶体管）12，其第一和第二发射体连接到HET16的第一发射极和数据输入端A 以及连接到电路11的输出端的反相器13.在没有基极的HET 14中，其集电极经由负载电阻15连接到电源线VCC，其第一发射极专门用于电流输出通过连接到HET16的集电极，其第二发射极连接到电源线VSS，其第二发射极通过直接连接到控制输入端S用于电流输入/输出，并且其第三发射极被专用用于通过连接到HET 17的第一发射器的电流输入，其第二发射极连接到数据输入端B.当控制数据S为高/低电平时，输出数据Q等于输入数据A / B 分别。

9. 发明授权

US5313117A Semiconductor logic circuit using two n-type negative resistance devices 失效
标题翻译：半导体逻辑电路使用两个n型负电阻器件
公开(公告)号：US5313117A
公开(公告)日：1994-05-17
申请号：US913108
申请日：1992-07-14
申请人： Koichi Maezawa
发明人： Koichi Maezawa
IPC分类号： H01L27/06 , H03K3/315 , H03K3/36 , H03K19/08 , H03K19/10 , H03K17/125
CPC分类号： B82Y10/00 , H01L27/0605 , H03K19/08 , H03K19/10 , H03K3/315 , H03K3/36
摘要： A semiconductor elements having N-type negative resistance characteristics are connected in series to obtain a series circuit. The two ends of the series circuit serve as drive voltage terminals to which periodic drive voltages are applied. At least one of the semiconductor elements has a control electrode to which a voltage is applied to change the peak current. A connection point between the two semiconductor elements serves as an output terminal.
摘要翻译：具有N型负电阻特性的半导体元件串联连接以获得串联电路。串联电路的两端用作施加周期性驱动电压的驱动电压端子。至少一个半导体元件具有施加电压以改变峰值电流的控制电极。两个半导体元件之间的连接点用作输出端子。

10. 发明授权

US11711069B2 Semiconductor integrated circuit 有权
公开(公告)号：US11711069B2
公开(公告)日：2023-07-25
申请号：US17696146
申请日：2022-03-16
申请人： SEIKO EPSON CORPORATION
发明人： Yoshiyuki Yamaguchi
IPC分类号： H03K3/011 , H03K3/0231 , H03L1/04 , H03K3/36 , H03L1/02
CPC分类号： H03K3/011 , H03K3/0231 , H03K3/36 , H03L1/026 , H03L1/04
摘要： Provided is a semiconductor integrated circuit including an oscillation circuit configured to output an oscillation signal, a heater configured to heat the oscillation circuit, a temperature sensor configured to detect a temperature of the oscillation circuit, and a nonvolatile memory configured to store temperature correction data. The oscillation circuit controls a frequency of the oscillation signal based on an output signal of the temperature sensor and the temperature correction data.

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