专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20190122715A1 Integrated Circuit Copy Prevention Device Powered By A Photoelectric Cell 审中-公开
公开(公告)号：US20190122715A1
公开(公告)日：2019-04-25
申请号：US15793046
申请日：2017-10-25
申请人： Qualcomm Incorporated
发明人： Peter RATHFELDER
IPC分类号： G11C8/20 , G06F12/14 , H01L21/822 , G11C11/41 , H01L23/00 , H01L31/048
CPC分类号： G11C8/20 , G06F12/1425 , G06F21/87 , G11C11/41 , H01L21/822 , H01L23/576 , H01L31/048
摘要： An integrated circuit includes a substrate, a first circuit disposed on the substrate, a photoelectric cell disposed on the substrate and coupled to the first circuit, the photoelectric cell to provide power to the first circuit when the photoelectric cell is exposed to light, and the first circuit to allow disabling at least a portion of the integrated circuit when powered by the photoelectric cell.

2. 发明申请

US20180240523A1 METHOD OF MANAGING SEMICONDUCTOR MEMORIES, CORRESPONDING INTERFACE, MEMORY AND DEVICE 审中-公开
公开(公告)号：US20180240523A1
公开(公告)日：2018-08-23
申请号：US15692158
申请日：2017-08-31
申请人： STMicroelectronics S.r.l.
发明人： Daniele MANGANO , Michele Alessandro CARRANO , Gaetano DI STEFANO , Roberto Sebastiano RUGGIRELLO
IPC分类号： G11C16/10 , G11C8/20 , G11C13/00
CPC分类号： G11C16/10 , G06F12/0246 , G06F12/0868 , G06F2212/214 , G06F2212/461 , G06F2212/7201 , G06F2212/7207 , G06F2212/7209 , G11C8/20 , G11C13/004 , G11C13/0069
摘要： A non-volatile data memory space for a range of user addresses is provided by means of a range of non-volatile flash memory locations for writing data. The range of flash memory locations for writing data is larger (e.g., 4 KB v. 100 B) than the range of user addresses. Data for a same user address may thus be written in different flash memory locations in a range of flash memory locations with data storage endurance correspondingly improved.

3. 发明授权

US09552857B1 Address generation circuit and semiconductor memory device including the same 有权
标题翻译：地址生成电路和包括其的半导体存储器件
公开(公告)号：US09552857B1
公开(公告)日：2017-01-24
申请号：US15210737
申请日：2016-07-14
申请人： SK hynix Inc.
发明人： Kyeong-Min Chae
IPC分类号： G11C29/00 , G11C8/18 , G11C8/04 , G11C8/20 , G11C8/06
CPC分类号： G11C8/18 , G11C8/04 , G11C8/06 , G11C8/20 , G11C29/70
摘要： An address generation circuit includes: a first address control clock generation unit suitable for generating a first address control clock signal in response to an internal clock signal; a second address control clock generation unit suitable for generating a second address control clock signal in response to one of an address initialization signal and the first address control clock signal; an address counting unit suitable for counting the second address control clock signal and generating a counting address; and a repair control unit suitable for latching the counting address in response to the second address control clock signal, comparing the latched counting address with a repair address, and generating a redundancy address based on the comparison result.
摘要翻译：地址产生电路包括：第一地址控制时钟生成单元，适于响应于内部时钟信号产生第一地址控制时钟信号; 第二地址控制时钟生成单元，适于响应于地址初始化信号和第一地址控制时钟信号之一产生第二地址控制时钟信号; 地址计数单元，适于对第二地址控制时钟信号进行计数并产生计数地址; 以及修复控制单元，其适于响应于所述第二地址控制时钟信号来锁存所述计数地址，将所述锁存的计数地址与修复地址进行比较，以及基于所述比较结果生成冗余地址。

4. 发明授权

US09406372B2 Secure non-volatile memory 有权
公开(公告)号：US09406372B2
公开(公告)日：2016-08-02
申请号：US13836690
申请日：2013-03-15
申请人： STMicroelectronics SA
发明人： Philippe Candelier , Laurent Dedieu , Noureddine Larhriq
IPC分类号： G11C11/00 , G11C11/419 , G11C7/24 , G11C8/20 , G11C11/41 , G11C16/22
CPC分类号： G11C11/419 , G11C7/24 , G11C8/20 , G11C11/41 , G11C16/22
摘要： A secure memory includes a bistable memory cell having a programmed start-up state, and means for flipping the state of the cell in response to a flip signal. The memory may include a clock for generating the flip signal with a period, for example, smaller than the acquisition time of an emission microscope.

5. 发明申请

US20160077911A1 METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR ADDRESS AND DATA INTEGRITY CHECKING IN FLASH MEMORY OPERATIONS 有权
标题翻译：闪存存储器操作中的地址和数据完整性检查的方法，系统和计算机可读介质
公开(公告)号：US20160077911A1
公开(公告)日：2016-03-17
申请号：US14486704
申请日：2014-09-15
申请人： SanDisk Technologies Inc.
发明人： Ashutosh Malshe , Karthik Krishnamoorthy
IPC分类号： G06F11/10 , G11C29/52
CPC分类号： G06F11/1068 , G06F11/1016 , G11C8/20 , G11C16/08 , G11C29/52 , G11C2029/0411
摘要： Methods, systems, and computer readable media for address and data integrity checking in flash memory operations are disclosed. One method includes, at a storage controller, generating, for an address unit, an address parity unit. The method further includes generating a command sequence including the address unit, the address parity unit, and an operation command specifying an operation to be performed on a flash memory array. The method further includes providing the command sequence to a flash memory device that includes the non-volatile memory array. The method further includes performing, by the flash memory device, an address integrity check on the address unit using the address parity unit. The method further includes determining whether or not to perform an operation specified by the command sequence based at least in part on a result of the address integrity check.
摘要翻译：公开了用于闪速存储器操作中的地址和数据完整性检查的方法，系统和计算机可读介质。一种方法包括在存储控制器处为地址单元生成地址奇偶校验单元。该方法还包括产生包括地址单元，地址奇偶校验单元和指定要对闪存阵列执行的操作的操作命令的命令序列。该方法还包括向包括非易失性存储器阵列的闪存器件提供命令序列。该方法还包括使用地址奇偶校验单元，通过闪存设备执行对地址单元的地址完整性检查。该方法还包括至少部分地基于地址完整性检查的结果来确定是否执行由命令序列指定的操作。

6. 发明授权

US09256523B2 Semiconductor storage device and control method thereof 有权
标题翻译：半导体存储装置及其控制方法
公开(公告)号：US09256523B2
公开(公告)日：2016-02-09
申请号：US14006296
申请日：2012-02-28
申请人： Ryousuke Takizawa
发明人： Ryousuke Takizawa
IPC分类号： G06F12/00 , G11C7/10 , G11C8/08 , G11C7/24 , G11C8/20 , G11C11/16 , G06F12/14
CPC分类号： G06F12/0238 , G06F3/0604 , G06F3/0644 , G06F3/0688 , G06F12/00 , G06F12/1416 , G06F12/1425 , G06F12/1441 , G06F2212/1016 , G06F2212/202 , G11C7/1009 , G11C7/24 , G11C8/08 , G11C8/20 , G11C11/1695
摘要： A memory includes a cell array including memory cells storing data, and a write driver writing data to the cells. A write driver performs or does not perform writing of write data according to write mask data input along with the write data. A multiplexer selectively outputs a write protect signal or the write mask data. The write protect signal is fixed to a command prohibiting the write data from being written. The command is included in the write mask data. A write protect controller controls the multiplexer to output the write protect signal when an address of a write protect area in the cell array matches an address of the write data. The write protect controller controls the multiplexer to output the write mask data as it is when the address of the write protect area in the cell array does not match the address of the write data.
摘要翻译：存储器包括包括存储数据的存储单元的单元阵列，以及写入驱动器向单元写入数据。写入驱动器根据与写入数据一起输入的写入掩码数据执行或不执行写入数据的写入。复用器选择性地输出写保护信号或写掩码数据。写保护信号固定为禁止写入数据写入的命令。该命令包含在写掩码数据中。写保护控制器控制多路复用器输出写保护信号，当单元阵列中写保护区的地址与写入数据的地址匹配时。写保护控制器控制多路复用器以当单元阵列中的写保护区域的地址与写入数据的地址不匹配时输出写掩码数据。

7. 发明授权

US09229639B2 Method and non-volatile memory device for improving latency together with write protection 有权
标题翻译：方法和非易失性存储器件，用于与写保护一起改善延迟
公开(公告)号：US09229639B2
公开(公告)日：2016-01-05
申请号：US13793209
申请日：2013-03-11
申请人： SANDISK TECHNOLOGIES INC.
发明人： Tal Rostoker
IPC分类号： G06F12/00 , G06F3/06 , G06F12/02 , G06F12/14 , G11C16/22 , G11C8/20
CPC分类号： G06F3/0611 , G06F3/0679 , G06F12/0246 , G06F12/1416 , G06F12/1425 , G06F12/1441 , G06F2212/1052 , G06F2212/2022 , G06F2212/7207 , G11C8/20 , G11C16/22
摘要： A data storage device includes a write protection data structure that includes a first set of entries corresponding to a first set of ranges of memory addresses. A first indication stored in an entry, in the first set of entries, corresponds to an absence of write-protected data between a lowest address of the range of addresses corresponding to the entry and a highest address of a memory. A second indication stored in the entry corresponds to write-protected data within the range of addresses. The data storage device also includes a write protection map that includes a second set of entries corresponding to a second set of ranges of the memory addresses. The device is configured to locate, in the write protection data structure, an entry corresponding to a range of memory addresses.
摘要翻译：数据存储设备包括写保护数据结构，其包括对应于第一组存储器地址范围的第一组条目。在第一组条目中存储在条目中的第一指示对应于在对应于条目的地址范围的最低地址和存储器的最高地址之间不存在写保护数据。存储在条目中的第二指示对应于地址范围内的写保护数据。数据存储设备还包括写保护地图，其包括对应于存储器地址的第二组范围的第二组条目。该设备被配置为在写保护数据结构中定位与存储器地址范围相对应的条目。

8. 发明授权

US09128620B2 Non-volatile memory with write protection data structure with write latency improvements 有权
标题翻译：具有写保护数据结构的非易失性存储器，具有写延迟改进
公开(公告)号：US09128620B2
公开(公告)日：2015-09-08
申请号：US14246479
申请日：2014-04-07
申请人： SANDISK TECHNOLOGIES INC.
发明人： Tal Rostoker
IPC分类号： G06F12/00 , G06F3/06 , G06F12/02 , G06F12/14 , G11C16/22 , G11C8/20
CPC分类号： G06F3/0611 , G06F3/0679 , G06F12/0246 , G06F12/1416 , G06F12/1425 , G06F12/1441 , G06F2212/1052 , G06F2212/2022 , G06F2212/7207 , G11C8/20 , G11C16/22
摘要： A data storage device includes a write protection data structure that includes a first set of entries corresponding to a first set of ranges of memory addresses. A first indication stored in an entry, in the first set of entries, corresponds to an absence of write-protected data between a lowest address of the range of addresses corresponding to the entry and a highest address of a memory. A second indication stored in the entry corresponds to write-protected data within the range of addresses. The data storage device also includes a write protection map that includes a second set of entries corresponding to a second set of ranges of the memory addresses. The device is configured to locate, in the write protection data structure, an entry corresponding to a range of memory addresses.
摘要翻译：数据存储设备包括写保护数据结构，其包括对应于第一组存储器地址范围的第一组条目。在第一组条目中存储在条目中的第一指示对应于在对应于条目的地址范围的最低地址和存储器的最高地址之间不存在写保护数据。存储在条目中的第二指示对应于地址范围内的写保护数据。数据存储设备还包括写保护地图，其包括对应于存储器地址的第二组范围的第二组条目。该设备被配置为在写保护数据结构中定位与存储器地址范围相对应的条目。

9. 发明授权

US09105344B2 Shut-off mechanism in an integrated circuit device 有权
标题翻译：集成电路设备中的关断机制
公开(公告)号：US09105344B2
公开(公告)日：2015-08-11
申请号：US13722496
申请日：2012-12-20
申请人： Kelin J Kuhn , Christopher J Jezewski , Marko Radosavljevic
发明人： Kelin J Kuhn , Christopher J Jezewski , Marko Radosavljevic
IPC分类号： G11C16/22
CPC分类号： G11C16/22 , G06F21/88 , G06F2221/2143 , G11C8/20
摘要： Described herein are technologies related to self-disabling feature of a integrated circuit device to avoid unauthorized access to stored data information.
摘要翻译：这里描述了与集成电路设备的自停功能相关的技术，以避免未经授权的访问存储的数据信息。

10. 发明申请

US20140269053A1 NONVOLATILE MEMORY DATA RECOVERY AFTER POWER FAILURE 有权
标题翻译：电源故障后的非易失性存储器数据恢复
公开(公告)号：US20140269053A1
公开(公告)日：2014-09-18
申请号：US13854263
申请日：2013-04-01
申请人： LSI CORPORATION
发明人： Zhengang Chen , Earl T. Cohen , Alex G. Tang
IPC分类号： G11C16/30
CPC分类号： G06F3/0619 , G06F3/0647 , G06F3/0679 , G11C7/24 , G11C8/20 , G11C11/5628 , G11C16/10 , G11C16/225 , G11C16/26
摘要： A method for data recovery after a power failure is disclosed. The method may include steps (A) to (D). Step (A) may determine that a last power-down of a solid-state drive was an unsafe power-down. Step (B) may search at least some of a plurality of pages of a nonvolatile memory of the solid-state drive to define an unsafe zone in response to the determining that the last power-down of the solid-state drive was the unsafe power-down. Step (C) may define a pad zone comprising one or more of the pages subsequent to the unsafe zone. Step (D) may resume operation of the solid-state drive by writing new data subsequent to the pad zone.
摘要翻译：公开了断电后的数据恢复方法。该方法可以包括步骤（A）至（D）。步骤（A）可以确定固态驱动器的最后断电是不安全的掉电。响应于确定固态驱动器的最后断电是不安全的电源，步骤（B）可以搜索固态驱动器的非易失性存储器的多个页面中的至少一些以定义不安全区域 -下。步骤（C）可以限定包括不安全区域之后的一个或多个页面的垫区域。步骤（D）可以通过在焊盘区域之后写入新的数据来恢复固态驱动器的操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式