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1. 发明授权

US10060966B2 Method and apparatus for enhancing guardbands using “in-situ” silicon measurements 有权
公开(公告)号：US10060966B2
公开(公告)日：2018-08-28
申请号：US14667365
申请日：2015-03-24
申请人： Intel Corporation
发明人： Sankaran M. Menon , Vasudev Bibikar
IPC分类号： H01L23/58 , G01R31/26 , G06F1/32 , H01L21/66
CPC分类号： G01R31/2637 , G01R31/2856 , G06F1/3203 , H01L22/34 , H01L23/58
摘要： A method and apparatus (e.g., semiconductor device) for setting voltages (e.g., guardbands) using “in situ,” or on-die, silicon measurements are described. In one embodiment the semiconductor device comprises: a process monitor to measure silicon parameters of the semiconductor device; and a controller coupled to the process monitor to set a voltage for use on at least a portion of the semiconductor device based on silicon process monitor measurements.

2. 发明申请

US20170350934A1 METHOD FOR ESTIMATING POWER SYSTEM HEALTH 审中-公开
公开(公告)号：US20170350934A1
公开(公告)日：2017-12-07
申请号：US15596878
申请日：2017-05-16
申请人： ROLLS-ROYCE plc
发明人： Mohamed Halick Mohamed SATHIK , Chandana Jayamapathi GAJANAYAKE , Shantha Dharmasiri Gamini JAYASINGHE , Amit Kumar GUPTA , Rejeki SIMANJORANG
IPC分类号： G01R31/26 , H02M3/158 , H02M7/217 , H02M7/537
CPC分类号： G01R31/2617 , G01R31/2621 , G01R31/2637 , G01R31/327 , G01R31/40 , H02M3/158 , H02M7/217 , H02M7/537
摘要： A method of monitoring the health of a semiconductor power electronic switch such as an insulated gate bipolar transistor (IGBT) is provided. The method having the steps of: measuring one or more parameters selected from the group consisting of: a rate of change of voltage ( dV dt ) across the switch; a rate of change of current ( di dt ) through the switch, a charge present on a gate of the switch (QG), a peak overshoot voltage (VPO) across the switch, and a peak overshoot or reverse recovery current (IRR) through the switch; and estimating the health of the switch based on the measured parameter(s).

3. 发明申请

US20170069552A1 ELECTRICAL COMPONENT TESTING IN STACKED SEMICONDUCTOR ARRANGEMENT 审中-公开
标题翻译：堆叠半导体布置中的电气部件测试
公开(公告)号：US20170069552A1
公开(公告)日：2017-03-09
申请号：US15354269
申请日：2016-11-17
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Shao-Yu Li , Hao-chieh Chan
IPC分类号： H01L21/66 , G01R31/26 , G01R31/28
CPC分类号： H01L22/22 , G01R31/2637 , G01R31/2644 , G01R31/2884 , G01R31/318513 , H01L22/14 , H01L22/34 , H01L27/0688
摘要： A stacked semiconductor arrangement is provided. The stacked semiconductor arrangement includes a dynamic pattern generator layer having an electrical component. The arrangement also includes a monitoring layer configured to evaluate electrical performance of the electrical component.
摘要翻译：提供堆叠式半导体装置。层叠的半导体装置包括具有电气部件的动态图案发生器层。该布置还包括被配置为评估电气部件的电性能的监控层。

4. 发明授权

US09502315B2 Electrical component testing in stacked semiconductor arrangement 有权
标题翻译：层叠半导体布置中的电气元件测试
公开(公告)号：US09502315B2
公开(公告)日：2016-11-22
申请号：US14560321
申请日：2014-12-04
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Shao-Yu Li , Hao-Chieh Chan
IPC分类号： H01L21/66 , H01L27/06 , G01R31/26 , G01R31/28 , G01R31/3185
CPC分类号： H01L22/22 , G01R31/2637 , G01R31/2644 , G01R31/2884 , G01R31/318513 , H01L22/14 , H01L22/34 , H01L27/0688
摘要： A stacked semiconductor arrangement is provided. The stacked semiconductor arrangement includes a dynamic pattern generator layer having an electrical component. The arrangement also includes a monitoring layer configured to evaluate electrical performance of the electrical component.
摘要翻译：提供堆叠式半导体装置。层叠的半导体装置包括具有电气部件的动态图案发生器层。该布置还包括被配置为评估电气部件的电性能的监控层。

5. 发明授权

US09354269B2 Semiconductor device and method of detecting wire open failure thereof 有权
标题翻译：半导体装置及其线路断开检测方法
公开(公告)号：US09354269B2
公开(公告)日：2016-05-31
申请号：US13964501
申请日：2013-08-12
申请人： FUJI ELECTRIC CO., LTD.
发明人： Shigemi Miyazawa
IPC分类号： G01R31/02 , G01R31/26 , H01L29/739 , G01R31/00 , H01L49/02 , H01L29/417 , H01L29/866 , G01R31/327 , H01L29/423
CPC分类号： G01R31/2632 , G01R31/006 , G01R31/026 , G01R31/2637 , G01R31/327 , H01L28/20 , H01L29/41741 , H01L29/42372 , H01L29/42376 , H01L29/7395 , H01L29/866 , H01L2224/0603 , H01L2224/48247 , H01L2224/49113 , H01L2924/13055 , H01L2924/00
摘要： In a semiconductor device, two series connections are arranged to be connected between respective split emitter electrodes and a gate electrode with Zener diode units connected in series to respective resistors, with the cathode sides thereof directed to the gate electrode side. The numbers of the Zener diodes in the Zener diode units in the respective series connections are different between the respective Zener diode units. Thus, a semiconductor device can be provided which is capable of detecting an open failure of a bonding wire regardless of the number of a plurality of the bonding wires connected in parallel, by a simple electrical test to make it possible to reliably sort out a semiconductor device with a wire open failure at an early stage.
摘要翻译：在半导体器件中，两个串联连接被布置成连接在相应的分离发射极和栅电极之间，齐纳二极管单元串联连接到相应的电阻器，其阴极侧指向栅电极侧。各个串联连接中齐纳二极管单元中齐纳二极管的数量在相应的齐纳二极管单元之间是不同的。因此，可以通过简单的电气测试来提供能够检测接合线的开路故障而不管并联连接的多个接合线的数量的半导体器件，以使得可以可靠地整理半导体装置在早期阶段有电线开路故障。

6. 发明申请

US20150226787A1 INSULATED-GATE BIPOLAR TRANSISTOR COLLECTOR-EMITTER SATURATION VOLTAGE MEASUREMENT 有权
标题翻译：绝缘栅双极晶体管集电极 - 发生器饱和电压测量
公开(公告)号：US20150226787A1
公开(公告)日：2015-08-13
申请号：US14175503
申请日：2014-02-07
申请人： Infineon Technologies AG
发明人： Michael Mankel , Carlos Castro-Serrato
IPC分类号： G01R31/26
CPC分类号： G01R31/2619 , G01K7/01 , G01K2217/00 , G01R31/2637
摘要： In one example, a method includes determining that an insulated-gate bipolar transistor (IGBT) is saturated, and while the IGBT is saturated, determining a collector-emitter saturation voltage (VCESat) of the IGBT.
摘要翻译：在一个示例中，一种方法包括确定绝缘栅双极晶体管（IGBT）饱和，并且当IGBT饱和时，确定IGBT的集电极 - 发射极饱和电压（VCESat）。

7. 发明授权

US09057756B2 Test apparatus 有权
标题翻译：测试仪器
公开(公告)号：US09057756B2
公开(公告)日：2015-06-16
申请号：US13292091
申请日：2011-11-09
申请人： Seiji Amanuma
发明人： Seiji Amanuma
IPC分类号： G01R31/08 , G01R31/02 , G01R31/26
CPC分类号： G01R31/2637 , G01R31/261
摘要： To prevent an excessive current from flowing through a device under test. A test apparatus that tests a device under test, comprising a power supply section that generates a power supply voltage to be supplied to the device under test; an inductive load section that is provided in a path leading from the power supply section to the device under test; a first semiconductor switch that is provided in the path leading from the inductive load section to the device under test and is connected in parallel with the device under test; and a control section that turns the first semiconductor switch ON when supply of the power supply voltage to the device under test is stopped.
摘要翻译：防止过电流流过被测设备。一种测试被测设备的测试装置，包括：电源部分，产生供应给被测设备的电源电压; 电感负载部，其设置在从供电部到被测设备的路径中; 第一半导体开关，其设置在从感性负载部分引导到被测器件的路径中，并与待测器件并联连接; 以及控制部，其在向被测试装置供给电源电压时，使第一半导体开关接通。

8. 发明授权

US08773144B2 Avalanche breakdown test apparatus 有权
标题翻译：雪崩击穿试验装置
公开(公告)号：US08773144B2
公开(公告)日：2014-07-08
申请号：US13253971
申请日：2011-10-06
申请人： Kenji Hashimoto
发明人： Kenji Hashimoto
IPC分类号： G01R31/26 , G01R31/00
CPC分类号： G01R31/2637 , G01R31/261
摘要： To detect whether energy accumulated in an inductive load section has been discharged. Provided is a test apparatus that tests a device under test, comprising a power supply section that generates a power supply voltage to be supplied to the device under test; an inductive load section that is provided in a path between the power supply section and the device under test; a housing section that houses a substrate that includes at least the inductive load section; and a lock maintaining section that keeps an opening/closing section, which allows an operator to access the substrate within the housing section, in a locked state when a voltage at a predetermined position on the substrate is greater than a set voltage.
摘要翻译：检测在感性负载部分中累积的能量是否已经放电。提供了一种测试被测设备的测试设备，包括：电源部分，其产生要供应到被测设备的电源电压; 电感负载部分，设置在电源部分和被测器件之间的路径中; 容纳部分，其容纳至少包括感性负载部分的衬底; 以及锁定保持部，其在基板上的预定位置处的电压大于设定电压时，在锁定状态下保持开闭部，其允许操作者在壳体部内进入基板。

9. 发明申请

US20120153977A1 TEST APPARATUS 审中-公开
标题翻译：测试仪器
公开(公告)号：US20120153977A1
公开(公告)日：2012-06-21
申请号：US13292091
申请日：2011-11-09
申请人： Seiji AMANUMA
发明人： Seiji AMANUMA
IPC分类号： G01R31/26
CPC分类号： G01R31/2637 , G01R31/261
摘要： To prevent an excessive current from flowing through a device under test. A test apparatus that tests a device under test, comprising a power supply section that generates a power supply voltage to be supplied to the device under test; an inductive load section that is provided in a path leading from the power supply section to the device under test; a first semiconductor switch that is provided in the path leading from the inductive load section to the device under test and is connected in parallel with the device under test; and a control section that turns the first semiconductor switch ON when supply of the power supply voltage to the device under test is stopped.
摘要翻译：防止过电流流过被测设备。一种测试被测设备的测试装置，包括：电源部分，产生供应给被测设备的电源电压; 电感负载部，其设置在从供电部到被测设备的路径中; 第一半导体开关，其设置在从感性负载部分引导到被测器件的路径中，并与待测器件并联连接; 以及控制部，其在向被测试装置供给电源电压时，使第一半导体开关接通。

10. 发明授权

US08188752B2 Yield improvement for Josephson junction test device formation 有权
标题翻译：约瑟夫逊结测试装置形成的产量提高
公开(公告)号：US08188752B2
公开(公告)日：2012-05-29
申请号：US12502640
申请日：2009-07-14
申请人： Mark B. Ketchen , Shwetank Kumar , Matthias Steffen , Christopher B. Lirakis , Richard Lazarus
发明人： Mark B. Ketchen , Shwetank Kumar , Matthias Steffen , Christopher B. Lirakis , Richard Lazarus
IPC分类号： G01R31/02
CPC分类号： G01R31/2637 , G01R27/2688
摘要： An apparatus for measuring component performance including a feed line having an input port and an output port, a first resonator connected to the feed line, a first Josephson junction device connected to the first resonator and to ground, and a second resonator connected to the feed line and to ground.
摘要翻译：一种用于测量部件性能的装置，包括具有输入端口和输出端口的馈线，连接到馈电线的第一谐振器，连接到第一谐振器和接地的第一约瑟夫逊结器件，以及连接到馈电线的第二谐振器线和地面。

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