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1. 发明授权

US09135215B1 Route prediction in packet switched networks 有权
标题翻译：分组交换网络中的路由预测
公开(公告)号：US09135215B1
公开(公告)日：2015-09-15
申请号：US12886163
申请日：2010-09-20
申请人： Ian Rudolf Bratt , Carl G. Ramey , Matthew Mattina
发明人： Ian Rudolf Bratt , Carl G. Ramey , Matthew Mattina
IPC分类号： H04L12/28 , G06F15/80 , H04L12/911
CPC分类号： G06F9/5022 , G06F9/4825 , G06F9/4881 , G06F9/544 , G06F11/1482 , G06F12/00 , G06F12/02 , G06F12/0806 , G06F12/0808 , G06F12/0844 , G06F12/0848 , G06F12/0864 , G06F12/0891 , G06F12/10 , G06F12/1027 , G06F12/12 , G06F12/121 , G06F12/123 , G06F13/4068 , G06F13/4221 , G06F15/16 , G06F15/8023 , G06F21/79 , G06F2212/502 , G06F2212/601 , H04L45/08 , H04L45/22 , H04L45/28 , H04L47/823 , H04L49/109
摘要： Communicating among nodes in a network includes: sending a packet from an origin node to a destination node over a route including plural nodes. At each node in the route, routing of the packet is initiated according to a predicted path concurrently with verifying the correctness of the predicted path based on analyzing route information in the packet. In response to results of verifying the correctness of the predicted path, the routing of the packet is completed according to the predicted path or initiating a routing of the packet according to an actual path based on the route information in the packet.
摘要翻译：在网络中的节点之间进行通信包括：通过包括多个节点的路由将分组从原始节点发送到目的地节点。在路由中的每个节点，基于分组中的路由信息，根据预测路径同时发起分组的路由，同时验证预测路径的正确性。响应于验证预测路径的正确性的结果，根据预测路径完成分组的路由，或者基于分组中的路由信息根据实际路径发起分组的路由。

2. 发明授权

US08934347B1 Low latency dynamic route selection 有权
标题翻译：低延迟动态路由选择
公开(公告)号：US08934347B1
公开(公告)日：2015-01-13
申请号：US12886346
申请日：2010-09-20
申请人： Ian Rudolf Bratt , Carl G. Ramey , Matthew Mattina
发明人： Ian Rudolf Bratt , Carl G. Ramey , Matthew Mattina
IPC分类号： G06F11/00
CPC分类号： G06F9/5022 , G06F9/4825 , G06F9/4881 , G06F9/544 , G06F11/1482 , G06F12/00 , G06F12/02 , G06F12/0806 , G06F12/0808 , G06F12/0844 , G06F12/0848 , G06F12/0864 , G06F12/0891 , G06F12/10 , G06F12/1027 , G06F12/12 , G06F12/121 , G06F12/123 , G06F13/4068 , G06F13/4221 , G06F15/16 , G06F15/8023 , G06F21/79 , G06F2212/502 , G06F2212/601 , H04L45/08 , H04L45/22 , H04L45/28 , H04L47/823 , H04L49/109
摘要： Communicating among cores in a computing system comprising a plurality of cores, each core comprising a processor and a switch, includes: routing a packet from a core or from a device coupled to at least one core to a destination over a route including one or more cores, with an order of dimensions associated with the route being selected dynamically upon construction of the packet; routing the packet to a first core in the route over the first selected dimension; and routing the packet from the first core to the destination over the second dimension.
摘要翻译：在包括多个核心的计算系统中的核心之间进行通信，每个核心包括处理器和交换机，包括：通过包括一个或多个路由的路由将来自核心或从耦合到至少一个核心的设备的分组路由到目的地核心，在构建分组时具有与路线相关联的维度顺序被动态地选择; 将所述分组路由到所述路由中的所述第一选定维度上的第一核心; 并且在第二维度上将分组从第一核心路由到目的地。

3. 发明授权

US08886899B1 Managing memory requests based on priority 有权
标题翻译：根据优先级管理内存请求
公开(公告)号：US08886899B1
公开(公告)日：2014-11-11
申请号：US12886050
申请日：2010-09-20
申请人： Liewei Bao
发明人： Liewei Bao
IPC分类号： G06F12/00 , G06F9/54 , G06F9/48
CPC分类号： G06F9/5022 , G06F9/4825 , G06F9/4881 , G06F9/544 , G06F11/1482 , G06F12/00 , G06F12/02 , G06F12/0806 , G06F12/0808 , G06F12/0844 , G06F12/0848 , G06F12/0864 , G06F12/0891 , G06F12/10 , G06F12/1027 , G06F12/12 , G06F12/121 , G06F12/123 , G06F13/4068 , G06F13/4221 , G06F15/16 , G06F15/8023 , G06F21/79 , G06F2212/502 , G06F2212/601 , H04L45/08 , H04L45/22 , H04L45/28 , H04L47/823 , H04L49/109
摘要： Managing access to an external memory in a computing system comprising one or more cores includes: receiving memory requests to access a memory at a memory controller coupled to at least one of the cores; assigning, by the memory controller, respective priorities to the memory requests, the priorities being based on priority configuration information; providing access, by the memory controller, to the memory based on the memory requests according to the assigned priorities. Messages are received at the memory controller to modify the priority configuration information.
摘要翻译：在包括一个或多个核心的计算系统中管理对外部存储器的访问包括：接收存储器请求以访问耦合到至少一个核的存储器控制器上的存储器; 由存储器控制器分配对存储器请求的优先级，优先级基于优先级配置信息; 根据分配的优先级，通过存储器控制器提供基于存储器请求到存储器的访问。在存储器控制器处接收消息以修改优先级配置信息。

4. 发明授权

US08635378B1 Flow control in a parallel processing environment 有权
标题翻译：在并行处理环境中的流量控制
公开(公告)号：US08635378B1
公开(公告)日：2014-01-21
申请号：US13229294
申请日：2011-09-09
申请人： David Wentzlaff
发明人： David Wentzlaff
IPC分类号： G06F15/80
CPC分类号： G06F13/4022 , G06F3/061 , G06F3/0656 , G06F3/0673 , G06F13/1673 , G06F13/4291 , G06F15/17337 , G06F15/17343
摘要： The flow of data in an integrated circuit is controlled. The integrated circuit comprising a plurality of tiles, each tile comprising a processor, a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles, and a receive buffer to store data from the switch. At a first tile, a count is maintained of data that has been sent to a second tile without receiving an acknowledgement up to a credit limit. At the second tile, data that arrives from the first tile when the receive buffer is full is sent to a memory outside of the tile.
摘要翻译：控制集成电路中的数据流。所述集成电路包括多个瓦片，每个瓦片包括处理器，包括切换电路的开关，所述切换电路将数据通过数据路径从其他瓦片转发到所述处理器以及其他瓦片的切换，以及接收缓冲器以存储来自所述开关的数据。在第一瓦片中，维持已发送到第二瓦片的数据的计数，而不接收到达信用限额的确认。在第二瓦片上，当接收缓冲器满时从第一瓦片到达的数据被发送到瓦片之外的存储器。

5. 发明授权

US08620940B1 Pattern matching 有权
标题翻译：模式匹配
公开(公告)号：US08620940B1
公开(公告)日：2013-12-31
申请号：US12977565
申请日：2010-12-23
申请人： Mathew Hostetter , Kenneth M. Steele , Vijay Aggarwal
发明人： Mathew Hostetter , Kenneth M. Steele , Vijay Aggarwal
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： G06F7/02 , G06F17/30985 , G06F2207/025
摘要： A method for processing data for pattern matching includes: receiving a first sequence of data values; and generating a second sequence of data values based on the first sequence and one or more patterns and history of data values in the first sequence, wherein the second sequence has fewer data values than the first sequence and all subsequences in the first sequence that match at least one of the one or more patterns are represented in the second sequence.
摘要翻译：一种用于处理模式匹配的数据的方法包括：接收第一数据值序列; 以及基于所述第一序列和所述第一序列中的数据值的一个或多个模式和历史来生成第二数据值序列，其中所述第二序列具有比所述第一序列更少的数据值，以及与所述第一序列匹配的所述第一序列中的所有子序列一个或多个图案中的至少一个在第二个序列中表示。

6. 发明授权

US08560780B1 Caching in multicore and multiprocessor architectures 有权
标题翻译：在多核和多处理器架构中进行缓存
公开(公告)号：US08560780B1
公开(公告)日：2013-10-15
申请号：US13553884
申请日：2012-07-20
申请人： Anant Agarwal , Ian R. Bratt , Matthew Mattina
发明人： Anant Agarwal , Ian R. Bratt , Matthew Mattina
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0815 , G06F12/0817
摘要： A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is configured to maintain at least a portion of the cache memory in which each cache line is dynamically managed as either local to the associated processor core or shared among multiple processor cores.
摘要翻译：多核处理器包括多个高速缓存存储器和多个处理器核心，每个处理器核心与高速缓冲存储器之一相关联。至少一些高速缓存存储器中的每一个被配置为保持高速缓冲存储器的至少一部分，其中每个高速缓存行被动态地管理为相关联的处理器核心的本地或在多个处理器核心之间共享。

7. 发明授权

US08327187B1 Low-overhead operating systems 有权
标题翻译：低架空操作系统
公开(公告)号：US08327187B1
公开(公告)日：2012-12-04
申请号：US12885978
申请日：2010-09-20
申请人： Christopher D. Metcalf
发明人： Christopher D. Metcalf
IPC分类号： G06F11/00
CPC分类号： G06F9/5022 , G06F9/4825 , G06F9/4881 , G06F9/544 , G06F11/1482 , G06F12/00 , G06F12/02 , G06F12/0806 , G06F12/0808 , G06F12/0844 , G06F12/0848 , G06F12/0864 , G06F12/0891 , G06F12/10 , G06F12/1027 , G06F12/12 , G06F12/121 , G06F12/123 , G06F13/4068 , G06F13/4221 , G06F15/16 , G06F15/8023 , G06F21/79 , G06F2212/502 , G06F2212/601 , H04L45/08 , H04L45/22 , H04L45/28 , H04L47/823 , H04L49/109
摘要： Managing processes in a computing system comprising one or more cores includes receiving a request for a first process on a first core to execute with at least one predetermined task of an operating system disabled on the first core. In response to the request, the operating system determines whether one or more potential errors in execution of one or more processes other than the first process executing on the first core would be caused by disabling the predetermined task on the first core. The operating system grants the request or rejects the request in response to determining whether one or more potential errors in execution of one or more processes other than the first process executing on the first core would be caused by disabling the predetermined task on the first core.
摘要翻译：在包括一个或多个核心的计算系统中的管理过程包括在第一核上接收对第一进程的请求，以执行在第一核上禁用的操作系统的至少一个预定任务。响应于该请求，操作系统确定在第一核上执行的第一进程之外的一个或多个进程的执行中的一个或多个潜在错误是否由第一内核上的预定任务禁用引起。响应于确定在第一核上执行的第一进程之外的一个或多个进程之外的一个或多个进程的执行中的一个或多个潜在错误是否由于禁用第一内核上的预定任务而导致的操作系统授予请求或拒绝该请求。

8. 发明授权

US08190855B1 Coupling data for interrupt processing in a parallel processing environment 有权
标题翻译：在并行处理环境中耦合中断处理数据
公开(公告)号：US08190855B1
公开(公告)日：2012-05-29
申请号：US12036918
申请日：2008-02-25
申请人： Carl G. Ramey , David Wentzlaff , Anant Agarwal
发明人： Carl G. Ramey , David Wentzlaff , Anant Agarwal
IPC分类号： G06F15/00
CPC分类号： G06F9/3885 , G06F9/30003 , G06F9/34 , G06F9/3824 , G06F9/3853 , G06F15/17381 , G06F15/8023 , H04L49/101 , H04L49/109 , H04L49/251
摘要： An integrated circuit comprises a plurality of tiles. Each tile comprises a processor, and a switch including switching circuitry to forward data received over data paths from other tiles to the processor and to switches of other tiles, and to forward data received from the processor to switches of other tiles. The integrated circuit further comprises one or more interface modules including circuitry to transfer data to and from a device external to the tiles; and a sub-port routing network including circuitry to route data between a port of a switch and a plurality of sub-ports coupled to one or more interface modules.
摘要翻译：集成电路包括多个瓦片。每个瓦片包括处理器和开关，其包括切换电路，用于将通过数据路径从其他瓦片接收的数据转发到处理器，并转换到其他瓦片，以及将从处理器接收的数据转发到其他瓦片的切换。集成电路还包括一个或多个接口模块，其包括用于将数据传送到和从外部的设备传输到数据块的电路; 以及子端口路由网络，其包括用于在交换机的端口与耦合到一个或多个接口模块的多个子端口之间路由数据的电路。

9. 发明授权

US08151088B1 Configuring routing in mesh networks 有权
标题翻译：配置网状网络中的路由
公开(公告)号：US08151088B1
公开(公告)日：2012-04-03
申请号：US12169456
申请日：2008-07-08
申请人： Liewei Bao , Ian Rudolf Bratt
发明人： Liewei Bao , Ian Rudolf Bratt
IPC分类号： G06F15/76 , G06F15/16 , G06F15/173
CPC分类号： G06F15/17312
摘要： A plurality of processor tiles are provided, each processor tile including a processor core. An interconnection network interconnects the processor cores and enables transfer of data among the processor cores. The interconnection network has a plurality of dimensions and is configurable to transmit data from an initial processor core or an input/output device to an intermediate processor core based on a first dimension ordering policy, and from the intermediate processor core to a destination processor core. The first dimension ordering policy specifies an ordering of the dimensions of the interconnection network when routing data through the interconnection network.
摘要翻译：提供多个处理器片，每个处理器片包括处理器核。互连网络将处理器核心互连，并实现处理器内核之间的数据传输。互连网络具有多个维度并且可配置为基于第一维排序策略以及从中间处理器核向目的地处理器核心将初始处理器内核或输入/输出设备的数据传输到中间处理器核心。第一维排序策略指定当通过互连网络路由数据时互连网络的维度的顺序。

10. 发明授权

US08117418B1 Method and system for managing virtual addresses of a plurality of processes corresponding to an application 失效
标题翻译：用于管理对应于应用的多个进程的虚拟地址的方法和系统
公开(公告)号：US08117418B1
公开(公告)日：2012-02-14
申请号：US12291605
申请日：2008-11-12
申请人： Chris Metcalf , Patrick Griffin
发明人： Chris Metcalf , Patrick Griffin
IPC分类号： G06F12/00 , G06F13/00 , G06F21/00 , G06F13/28 , G06F9/26 , G06F9/34 , G06F9/46
CPC分类号： G06F9/52 , G06F9/5016 , G06F12/1036 , G06F12/126 , G06F21/79
摘要： The present invention provides a method and system for managing virtual addresses of a plurality of processes corresponding to an application. The method comprises designating a first set of ranges of virtual addresses to the plurality of processes, wherein the virtual addresses of the first set of ranges map to a memory region shared among the plurality of processes. Further, the method comprises designating a second set of ranges of virtual addresses to the plurality of processes, wherein the virtual addresses of the second set of ranges map to a memory region independently used by a process of the plurality of processes. Furthermore, the method comprises adding or removing virtual address ranges from one of the first set of ranges and the second set of ranges based on requirements of the application, wherein the addition or removal is performed in virtual addresses of the plurality of processes.
摘要翻译：本发明提供一种用于管理与应用相对应的多个进程的虚拟地址的方法和系统。该方法包括为多个进程指定第一组虚拟地址范围，其中第一组范围的虚拟地址映射到在多个进程之间共享的存储器区域。此外，该方法包括为多个进程指定第二组虚拟地址范围，其中第二组范围的虚拟地址映射到由多个进程的处理独立使用的存储器区域。此外，该方法包括基于应用的需求来添加或去除第一组范围和第二组范围中的虚拟地址范围，其中在多个进程的虚拟地址中执行添加或删除。

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