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    • 3. 发明申请
    • DISPLAY APPARATUS AND INSPECTION METHOD
    • 显示装置和检查方法
    • US20060226866A1
    • 2006-10-12
    • US11425449
    • 2006-06-21
    • Naoki Ando
    • Naoki Ando
    • G01R31/00
    • G09G3/006G09G3/3666Y10S345/904
    • The test circuit of a display apparatus according to the invention detect short-circuiting in each of the data lines Dn by inputting the electric potential Vd of the data line Dn connected to the corresponding one of high resistance first short-circuiting detecting resistors Tr1n connecting a predetermined electric potential and the data line Dn to the corresponding one of first detector logic circuits and binarizing and outputting the input electric potential Vd of the data line Dn by referring to a predetermined threshold value and also detect short-circuiting in each of the gate lines Gm by inputting the electric potential of the gate line Gm connected to the corresponding one of high resistance second short-circuiting detecting resistors connecting a predetermined electric potential and the gate line Gm to the corresponding one of second detector logic circuits and binarizing and outputting the input electric potential of the gate line by referring to a predetermined threshold value. The defects (short-circuits) produced in the process of manufacturing the display apparatus can be inspected by a simple technique.
    • 根据本发明的显示装置的测试电路通过输入连接到连接到第一短路检测电阻器的高电阻第一短路检测电阻器Tr1n中的相应一个的数据线Dn的电位Vd来检测每条数据线Dn中的短路 预定电位和数据线Dn耦合到第一检测器逻辑电路中的相应一个,并参考预定阈值二值化并输出数据线Dn的输入电位Vd,并且还检测每条栅极线中的短路 通过将连接到连接预定电位的高电阻第二短路检测电阻器和栅极线Gm的相应一个的栅极线Gm的电位输入到第二检测器逻辑电路中的相应一个,并将二进制输出 通过参照预定的阈值进行栅极线的电位 e。 可以通过简单的技术检查制造显示装置的过程中产生的缺陷(短路)。
    • 8. 发明授权
    • Display apparatus and inspection method
    • 显示装置和检查方法
    • US07358757B2
    • 2008-04-15
    • US11425449
    • 2006-06-21
    • Naoki Ando
    • Naoki Ando
    • G01R31/00
    • G09G3/006G09G3/3666Y10S345/904
    • The test circuit of a display apparatus according to the invention detect short-circuiting in each of the data lines Dn by inputting the electric potential Vd of the data line Dn connected to the corresponding one of high resistance first short-circuiting detecting resistors Tr1n connecting a predetermined electric potential and the data line Dn to the corresponding one of first detector logic circuits and binarizing and outputting the input electric potential Vd of the data line Dn by referring to a predetermined threshold value and also detect short-circuiting in each of the gate lines Gm by inputting the electric potential of the gate line Gm connected to the corresponding one of high resistance second short-circuiting detecting resistors connecting a predetermined electric potential and the gate line Gm to the corresponding one of second detector logic circuits and binarizing and outputting the input electric potential of the gate line by referring to a predetermined threshold value. The defects (short-circuits) produced in the process of manufacturing the display apparatus can be inspected by a simple technique.
    • 根据本发明的显示装置的测试电路通过输入连接到连接到第一短路检测电阻器的高电阻第一短路检测电阻器Tr1n中的相应一个的数据线Dn的电位Vd来检测每条数据线Dn中的短路 预定电位和数据线Dn耦合到第一检测器逻辑电路中的相应一个,并参考预定阈值二值化并输出数据线Dn的输入电位Vd,并且还检测每条栅极线中的短路 通过将连接到连接预定电位的高电阻第二短路检测电阻器和栅极线Gm的相应一个的栅极线Gm的电位输入到第二检测器逻辑电路中的相应一个,并将二进制输出 通过参照预定的阈值进行栅极线的电位 e。 可以通过简单的技术检查制造显示装置的过程中产生的缺陷(短路)。
    • 9. 发明申请
    • Inspection method semiconductor device and display device
    • 检验方法半导体器件及显示装置
    • US20060192752A1
    • 2006-08-31
    • US10565177
    • 2004-07-16
    • Naoki Ando
    • Naoki Ando
    • G09G5/00
    • G09G3/006G09G3/3677G09G3/3688G09G2330/12
    • The present invention allows an efficient test as to the presence of line defects in data lines and gate lines in a liquid crystal display. A logic circuit for a test is provided according to the interconnect layout structure on a semiconductor substrate of a liquid crystal display, and ends of data lines are coupled to inputs of the logic circuit. At the time of the test, test drive signals corresponding to a certain logical value are applied to the data lines, and a determination is made as to defects in the data lines based on the output from the logic circuit, obtained in response to the signal application. This way means that determinations can be made as to defects in the data lines based on a logical value as the output from the logic circuit, i.e., binary values. Such a configuration is also applied to gate lines.
    • 本发明允许对液晶显示器中的数据线和栅极线中的线缺陷的存在进行有效的测试。 根据液晶显示器的半导体衬底上的互连布局结构提供用于测试的逻辑电路,并且数据线的端部耦合到逻辑电路的输入。 在测试时,将对应于某一逻辑值的测试驱动信号应用于数据线,并根据逻辑电路的输出响应于该信号而确定数据线中的缺陷 应用。 这意味着可以基于作为来自逻辑电路的输出的逻辑值(即二进制值)来确定数据线中的缺陷。 这种配置也适用于栅极线。
    • 10. 发明授权
    • Driver and driving method, and display device
    • 驱动和驱动方法,以及显示装置
    • US08139051B2
    • 2012-03-20
    • US12017679
    • 2008-01-22
    • Naoki Ando
    • Naoki Ando
    • G09G3/36
    • G09G3/006G09G3/3648G09G2300/0408G09G2300/0426
    • The present invention provides a driver, including: data lines disposed in parallel with each other; gate lines disposed in parallel with each other and at right angles to the data lines so as to be electrically insulated from the data lines; odd-numbered pixel cell connected to the odd-numbered data line from the head one, and the odd-numbered gate line from the head one; even-numbered pixel cell connected to the even-numbered data line from the head one, and the even-numbered gate line from the head one; driving means for driving the odd-numbered gate lines and the even-numbered gate lines independently of each other; inputting means for inputting a signal having a predetermined potential to each of the odd-numbered gate lines and the even-numbered gate lines; and comparing means for comparing potentials of the each adjacent odd-numbered data line and even-numbered data line with each other, and outputting a comparison result.
    • 本发明提供一种驱动器,包括:彼此平行设置的数据线; 栅极线彼此平行设置并与数据线成直角,从而与数据线电绝缘; 从头一连接到奇数编号数据线的奇数像素单元,以及来自头一的奇数编号的栅极线; 从头一连接到偶数数据线的偶数像素单元和来自头​​一的偶数编号的栅极线; 驱动装置,用于彼此独立地驱动奇数编号的栅极线和偶数栅极线; 输入装置,用于向每个奇数编号的栅极线和偶数的栅极线输入具有预定电位的信号; 以及比较装置,用于将每个相邻的奇数数据线和偶数数据线的电位相互比较,并输出比较结果。