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1. 发明授权

US09041008B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09041008B2
公开(公告)日：2015-05-26
申请号：US13411789
申请日：2012-03-05
申请人： Yukio Nakabayashi , Takashi Shinohe , Atsuko Yamashita
发明人： Yukio Nakabayashi , Takashi Shinohe , Atsuko Yamashita
IPC分类号： H01L29/78 , H01L29/66 , H01L21/04
CPC分类号： H01L29/66068 , H01L21/046 , H01L21/0475 , H01L29/7827
摘要： A semiconductor device of an embodiment includes a first conductive type silicon carbide substrate having first and second main surfaces, a first conductive type silicon carbide layer formed on the first main surface, a second conductive type first silicon carbide region formed in the silicon carbide layer, and a first conductive type second silicon carbide region formed in the first silicon carbide region. The device includes a trench penetrating through the first and second silicon carbide regions, and a second conductive type third silicon carbide region formed on a bottom and a side surface of the trench. The third silicon carbide region is in contact with the first silicon carbide region, and is formed between the trench and the silicon carbide layer. In addition, the device includes a gate insulating film formed in the trench, a gate electrode, a first electrode, and a second electrode.
摘要翻译：实施例的半导体器件包括具有第一和第二主表面的第一导电型碳化硅衬底，形成在第一主表面上的第一导电型碳化硅层，形成在碳化硅层中的第二导电型第一碳化硅区，以及形成在第一碳化硅区域中的第一导电类型的第二碳化硅区域。该器件包括穿过第一和第二碳化硅区域的沟槽以及形成在沟槽的底部和侧表面上的第二导电类型的第三碳化硅区域。第三碳化硅区域与第一碳化硅区域接触，并且形成在沟槽和碳化硅层之间。此外，该器件包括形成在沟槽中的栅极绝缘膜，栅电极，第一电极和第二电极。

2. 发明授权

US08569795B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08569795B2
公开(公告)日：2013-10-29
申请号：US13217472
申请日：2011-08-25
申请人： Hiroshi Kono , Yukio Nakabayashi , Takashi Shinohe , Makoto Mizukami
发明人： Hiroshi Kono , Yukio Nakabayashi , Takashi Shinohe , Makoto Mizukami
IPC分类号： H01L33/32 , H01L29/80 , H01L29/16 , H01L27/11 , H01L27/10
CPC分类号： H01L29/7802 , H01L21/049 , H01L29/0623 , H01L29/1608 , H01L29/4236 , H01L29/45 , H01L29/4966 , H01L29/66068 , H01L29/7813
摘要： A semiconductor device of an embodiment includes: a silicon carbide substrate including first and second principal surfaces; a first conductive-type first silicon carbide layer provided on the first principal surface of the silicon carbide substrate; a second conductive-type first silicon carbide region formed on a surface of the first silicon carbide layer; a first conductive-type second silicon carbide region formed on a surface of the first silicon carbide region; a second conductive-type third silicon carbide region formed on the surface of the first silicon carbide region; a gate insulating film continuously formed on the surfaces of the first silicon carbide layer, the first silicon carbide region, and the second silicon carbide region; a first electrode formed of silicon carbide formed on the gate insulating film; a second electrode formed on the first electrode; an interlayer insulating film for covering the first and second electrodes; a third electrode electrically connected to the second silicon carbide region and the third silicon carbide region; and a fourth electrode formed on the second principal surface of the silicon carbide substrate.
摘要翻译：实施例的半导体器件包括：碳化硅衬底，其包括第一和第二主表面; 设置在碳化硅衬底的第一主表面上的第一导电型第一碳化硅层; 形成在所述第一碳化硅层的表面上的第二导电型第一碳化硅区; 形成在所述第一碳化硅区域的表面上的第一导电型第二碳化硅区域; 形成在所述第一碳化硅区域的表面上的第二导电型第三碳化硅区域; 连续形成在所述第一碳化硅层，所述第一碳化硅区域和所述第二碳化硅区域的表面上的栅极绝缘膜; 形成在所述栅极绝缘膜上的由碳化硅形成的第一电极; 形成在第一电极上的第二电极; 用于覆盖第一和第二电极的层间绝缘膜; 电连接到第二碳化硅区域和第三碳化硅区域的第三电极; 以及形成在碳化硅衬底的第二主表面上的第四电极。

3. 发明申请

US20120228631A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120228631A1
公开(公告)日：2012-09-13
申请号：US13217472
申请日：2011-08-25
申请人： Hiroshi KONO , Yukio Nakabayashi , Takashi Shinohe , Makoto Mizukami
发明人： Hiroshi KONO , Yukio Nakabayashi , Takashi Shinohe , Makoto Mizukami
IPC分类号： H01L29/24 , H01L29/78
CPC分类号： H01L29/7802 , H01L21/049 , H01L29/0623 , H01L29/1608 , H01L29/4236 , H01L29/45 , H01L29/4966 , H01L29/66068 , H01L29/7813
摘要： A semiconductor device of an embodiment includes: a silicon carbide substrate including first and second principal surfaces; a first conductive-type first silicon carbide layer provided on the first principal surface of the silicon carbide substrate; a second conductive-type first silicon carbide region formed on a surface of the first silicon carbide layer; a first conductive-type second silicon carbide region formed on a surface of the first silicon carbide region; a second conductive-type third silicon carbide region formed on the surface of the first silicon carbide region; a gate insulating film continuously formed on the surfaces of the first silicon carbide layer, the first silicon carbide region, and the second silicon carbide region; a first electrode formed of silicon carbide formed on the gate insulating film; a second electrode formed on the first electrode; an interlayer insulating film for covering the first and second electrodes; a third electrode electrically connected to the second silicon carbide region and the third silicon carbide region; and a fourth electrode formed on the second principal surface of the silicon carbide substrate.
摘要翻译：实施例的半导体器件包括：碳化硅衬底，其包括第一和第二主表面; 设置在碳化硅衬底的第一主表面上的第一导电型第一碳化硅层; 形成在所述第一碳化硅层的表面上的第二导电型第一碳化硅区; 形成在所述第一碳化硅区域的表面上的第一导电型第二碳化硅区域; 形成在所述第一碳化硅区域的表面上的第二导电型第三碳化硅区域; 连续形成在所述第一碳化硅层，所述第一碳化硅区域和所述第二碳化硅区域的表面上的栅极绝缘膜; 形成在所述栅极绝缘膜上的由碳化硅形成的第一电极; 形成在第一电极上的第二电极; 用于覆盖第一和第二电极的层间绝缘膜; 电连接到第二碳化硅区域和第三碳化硅区域的第三电极; 以及形成在碳化硅衬底的第二主表面上的第四电极。

4. 发明申请

US20120146053A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120146053A1
公开(公告)日：2012-06-14
申请号：US13237697
申请日：2011-09-20
申请人： Masumi SAITOH , Toshinori Numata , Yukio Nakabayashi , Kensuke Ota
发明人： Masumi SAITOH , Toshinori Numata , Yukio Nakabayashi , Kensuke Ota
IPC分类号： H01L29/161 , H01L21/336 , H01L29/78
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7843
摘要： A semiconductor device according to an embodiment includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, first gate sidewalls formed on both sides of the gate electrode, and a source/drain semiconductor layer formed on the semiconductor substrate to sandwich the first gate sidewalls with the gate electrode. Further, second gate sidewalls are provided on the first gate sidewalls and the source/drain semiconductor layer at both sides of the gate electrode, wherein the boundary of each of the second gate sidewalls with each of the first gate sidewalls is terminated at the side surface of the gate electrode, and each of the second gate sidewalls has a smaller Young's modulus and a lower dielectric constant than each of the first gate sidewalls.
摘要翻译：根据实施例的半导体器件包括半导体衬底，形成在半导体衬底上的栅极绝缘膜，形成在栅极绝缘膜上的栅电极，形成在栅电极两侧的第一栅极侧壁和源极/漏极半导体层，形成在半导体衬底上，以与栅电极夹住第一栅极侧壁。此外，第二栅极侧壁设置在栅电极两侧的第一栅极侧壁和源极/漏极半导体层上，其中每个第二栅极侧壁与每个第一栅极侧壁的边界在侧表面终止并且每个第二栅极侧壁具有比每个第一栅极侧壁更小的杨氏模量和更低的介电常数。

5. 发明授权

US07521752B2 Fin-type channel transistor and method of manufacturing the same 失效
标题翻译：鳍型沟道晶体管及其制造方法
公开(公告)号：US07521752B2
公开(公告)日：2009-04-21
申请号：US11384269
申请日：2006-03-21
申请人： Atsuhiro Kinoshita , Junji Koga , Yukio Nakabayashi
发明人： Atsuhiro Kinoshita , Junji Koga , Yukio Nakabayashi
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/088 , H01L21/823412 , H01L21/823437 , H01L21/84 , H01L27/1203 , H01L29/41733 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L29/78618
摘要： It is possible to reliably implant an impurity into an impurity forming region, and to form a self-aligned silicides on the entire portion of the source and drain regions. There are provided: a first semiconductor layer of a first conductivity type in a substantially a rectangular solid shape formed on a substrate; a gate electrode formed on a pair of first side portions of the first semiconductor layer facing to each other with a gate insulating film being placed between the gate electrode and the first side portions; a second semiconductor layer of the first conductivity type connected to bottom portions of a pair of second side portions of the first semiconductor layer placed in a substantially perpendicular direction with respect to the first side portions, the second semiconductor layer extending along the substantially perpendicular direction; a first impurity region of a second conductivity type formed in the second semiconductor layer; second impurity regions formed on the pair of side portions of the first semiconductor layer and connected to the first impurity region; and a channel region formed between the second impurity regions of the first semiconductor layer.
摘要翻译：可以将杂质可靠地注入到杂质形成区域中，并且在源极和漏极区域的整个部分上形成自对准的硅化物。提供：形成在基板上的基本为矩形的实心形状的第一导电类型的第一半导体层; 形成在所述第一半导体层的一对第一侧部分上的栅电极，栅极绝缘膜位于所述栅电极和所述第一侧部之间，所述栅极绝缘膜彼此面对; 所述第一导电类型的第二半导体层连接到所述第一半导体层的一对第二侧部的与所述第一侧部大致垂直的方向上的第二侧部的底部，所述第二半导体层沿着大致垂直的方向延伸; 形成在第二半导体层中的第二导电类型的第一杂质区; 第二杂质区，形成在第一半导体层的一对侧部并连接到第一杂质区; 以及形成在第一半导体层的第二杂质区之间的沟道区。

6. 发明申请

US20080227241A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20080227241A1
公开(公告)日：2008-09-18
申请号：US12043327
申请日：2008-03-06
申请人： Yukio Nakabayashi , Junji Koga , Atsuhiro Kinoshita
发明人： Yukio Nakabayashi , Junji Koga , Atsuhiro Kinoshita
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L21/823807 , H01L21/845 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/045 , H01L29/66795
摘要： A semiconductor device fabrication method for forming on a wafer-bonded substrate p- and n-type FinFETs each having a channel plane exhibiting high carrier mobility is disclosed. First, prepare two semiconductor wafers. Each wafer has a surface of {100} crystalline orientation and a direction. These wafers are surface-bonded together so that the directions of upper and lower wafers cross each other at a rotation angle, thereby providing a “hybrid” crystal-oriented substrate. On this substrate, form semiconductor regions, one of which is identical in direction to the upper wafer, and the other of which is equal in direction to the lower wafer. In the one region, form a pFinFET having {100} channel plane. In the other region, form an nFinFET having its channel direction in parallel or perpendicular to that of the pFinFET. A CMOS FinFET structure is thus obtained.
摘要翻译：公开了一种半导体器件制造方法，用于在晶片结合的衬底上形成各自具有表现出高载流子迁移率的沟道平面的p型和n型FinFET。首先，准备两个半导体晶圆。每个晶片具有{100}晶体取向和<110>方向的表面。这些晶片被表面粘合在一起，使得上下晶片的<110>方向以旋转角彼此交叉，从而提供“混合”的晶体取向基板。在该衬底上，形成半导体区域，其中一个在<110>方向上与上晶片相同，另一个在<110>方向与下晶片相等。在一个区域中，形成具有{100}通道平面的pFinFET。在另一区域，形成其通道方向平行或垂直于pFinFET的nFinFET。由此获得CMOS FinFET结构。

7. 发明授权

US08467241B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US08467241B2
公开(公告)日：2013-06-18
申请号：US13246996
申请日：2011-09-28
申请人： Jun Fujiki , Kiwamu Sakuma , Naoki Yasuda , Yukio Nakabayashi , Masumi Saitoh
发明人： Jun Fujiki , Kiwamu Sakuma , Naoki Yasuda , Yukio Nakabayashi , Masumi Saitoh
IPC分类号： G11C11/34
CPC分类号： H01L29/792 , G11C16/0466 , H01L27/11568 , H01L29/4234
摘要： In a semiconductor layer, information is written by applying a first potential to a first electrode, applying a second potential that is lower than the first potential to all of back gate electrodes, applying a third potential that is higher than the first potential to the first to (i−1)th front gate electrodes, and applying a fourth potential that is between the second and third potentials to the ith and subsequent front gate electrodes, where “i” is a positive integer and identifies a specific location to which information is to be written.
摘要翻译：在半导体层中，通过向第一电极施加第一电位，向所有背栅电极施加低于第一电位的第二电位，向第一电极施加高于第一电位的第三电位，写入信息到（i-1）个前栅电极，并且将第二和第三电位之间的第四电位施加到第i个和后续的前栅电极，其中“i”是正整数，并且识别信息的特定位置要写

8. 发明申请

US20120282743A1 SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权
标题翻译：半导体器件制造方法
公开(公告)号：US20120282743A1
公开(公告)日：2012-11-08
申请号：US13487295
申请日：2012-06-04
申请人： Masumi SAITOH , Toshinori Numata , Yukio Nakabayashi
发明人： Masumi SAITOH , Toshinori Numata , Yukio Nakabayashi
IPC分类号： H01L21/336
CPC分类号： H01L27/0207 , H01L21/266 , H01L21/823437 , H01L21/823462 , H01L21/845 , H01L27/1211 , H01L29/66628 , H01L29/785
摘要： In a semiconductor device manufacturing method, a first semiconductor region which includes a narrow portion and a wide portion is formed in an upper portion of a semiconductor substrate, a gate insulating film is formed on at least side surfaces of the narrow portion, a gate electrode is formed on the gate insulating film, a mask pattern that covers the wide portion is formed, ion implantation of an impurity is performed with the mask pattern as a mask to form an extension impurity region in the narrow portion, the mask pattern is removed, a heat treatment is performed to activate the impurity, a gate sidewall is formed on a side surface of the gate electrode, epitaxial growth of a semiconductor film is performed on the narrow portion and the wide portion after the formation of the gate sidewall, and source-drain regions is formed on both sides of the gate electrode.
摘要翻译：在半导体器件制造方法中，在半导体衬底的上部形成包括窄部分和宽部分的第一半导体区域，在所述窄部分的至少侧表面上形成栅极绝缘膜，栅电极形成在栅极绝缘膜上，形成覆盖该宽部的掩模图形，利用掩模图案作为掩模进行杂质的离子注入，以在狭窄部分形成延伸杂质区，除去掩模图案，执行热处理以激活杂质，在栅电极的侧表面上形成栅极侧壁，在形成栅极侧壁的狭窄部分和宽部分之后进行半导体膜的外延生长，源在栅电极的两侧形成有引线区域。

9. 发明申请

US20060199310A1 Semiconductor integrated circuit and semiconductor device 审中-公开
标题翻译：半导体集成电路和半导体器件
公开(公告)号：US20060199310A1
公开(公告)日：2006-09-07
申请号：US11366552
申请日：2006-03-03
申请人： Yukio Nakabayashi , Junji Koga
发明人： Yukio Nakabayashi , Junji Koga
IPC分类号： H01L21/82 , H01L23/02
CPC分类号： H01L25/0657 , H01L21/76834 , H01L21/76852 , H01L21/8221 , H01L21/823807 , H01L21/84 , H01L23/057 , H01L23/13 , H01L24/48 , H01L25/105 , H01L25/50 , H01L27/0688 , H01L27/1203 , H01L29/7842 , H01L29/7849 , H01L29/78603 , H01L2224/48091 , H01L2224/48227 , H01L2225/0651 , H01L2225/06541 , H01L2225/06582 , H01L2225/1052 , H01L2924/00014 , H01L2924/01079 , H01L2924/01322 , H01L2924/12032 , H01L2924/12044 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/1627 , H01L2924/3511 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor integrated circuit includes a substrate having a main surface to which a first stress is applied; a first channel conductive field effect transistor placed in a first region of the main surface of the substrate, the carrier mobility of a channel of the first channel conductive field effect transistor being improved by the first stress; and a second channel conductive field effect transistor placed in a second region of the main surface of the substrate, and receiving a second stress at a channel thereof, the second stress being opposite to the first stress, the carrier mobility of the channel of the second channel conductive field effect transistor being improved by the second stress, and the second region being independent from the first region.
摘要翻译：半导体集成电路包括具有施加第一应力的主表面的基板; 放置在基板的主表面的第一区域中的第一沟道导电场效应晶体管，通过第一应力改善第一沟道导电场效应晶体管的沟道的载流子迁移率; 以及放置在所述基板的主表面的第二区域中的第二沟道导电场效应晶体管，并且在其沟道处接收第二应力，所述第二应力与所述第一应力相反，所述第二应变的沟道的载流子迁移率沟道导电场效应晶体管被第二应力改善，第二区域独立于第一区域。

10. 发明授权

US08932915B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08932915B2
公开(公告)日：2015-01-13
申请号：US13082103
申请日：2011-04-07
申请人： Masumi Saitoh , Toshinori Numata , Yukio Nakabayashi
发明人： Masumi Saitoh , Toshinori Numata , Yukio Nakabayashi
IPC分类号： H01L29/772 , H01L21/336 , B82Y10/00 , H01L21/84 , H01L27/06 , H01L27/115 , H01L27/12 , H01L29/04 , H01L29/06 , H01L29/66 , H01L29/775 , H01L29/78 , H01L29/792 , H01L21/8238 , H01L27/092
CPC分类号： H01L29/66765 , B82Y10/00 , H01L21/823821 , H01L21/84 , H01L21/845 , H01L27/0688 , H01L27/092 , H01L27/11578 , H01L27/11582 , H01L27/1203 , H01L27/1211 , H01L29/04 , H01L29/0673 , H01L29/66439 , H01L29/66666 , H01L29/66833 , H01L29/775 , H01L29/7827 , H01L29/7843 , H01L29/7847 , H01L29/78669 , H01L29/78678 , H01L29/792
摘要： A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer.
摘要翻译：实施例的半导体器件制造方法包括以下步骤：在半导体衬底上形成第一绝缘层; 在第一绝缘层上形成具有窄部分的非晶或多晶半导体层; 在所述半导体层上形成具有大于所述半导体层的热膨胀系数的热膨胀系数的第二绝缘层; 进行热处理; 去除所述第二绝缘层; 在所述窄部的侧面上形成栅极绝缘膜; 在栅极绝缘膜上形成栅电极; 以及在所述半导体层中形成源 - 漏区。

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