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1. 发明申请

US20120292719A1 HIGH-K METAL GATE DEVICE 有权
标题翻译：高K金属门装置
公开(公告)号：US20120292719A1
公开(公告)日：2012-11-22
申请号：US13110922
申请日：2011-05-19
申请人： Young Way TEH , Michael V. AQUILINO , Arifuzzaman (Arif) SHEIKH , Yun Ling TAN , Hao ZHANG , Deleep R. NAIR , Jinghong H. (John) LI
发明人： Young Way TEH , Michael V. AQUILINO , Arifuzzaman (Arif) SHEIKH , Yun Ling TAN , Hao ZHANG , Deleep R. NAIR , Jinghong H. (John) LI
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L21/28114 , H01L29/42376 , H01L29/4966 , H01L29/518
摘要： A device includes a substrate with a device region surrounded by an isolation region, in which the device region includes edge portions along a width of the device region and a central portion. The device further includes a gate layer disposed on the substrate over the device region, in which the gate layer includes a graded thickness in which the gate layer at edge portions of the device region has a thickness TE that is different from a thickness TC at the central portion of the device region.
摘要翻译：一种器件包括具有由隔离区域围绕的器件区域的衬底，其中器件区域包括沿着器件区域的宽度的边缘部分和中心部分。该器件还包括在器件区域上设置在衬底上的栅极层，其中栅极层包括梯度厚度，其中器件区域的边缘部分处的栅极层的厚度TE不同于设备区域的中心部分。

2. 发明申请

US20140061862A1 SEMICONDUCTOR FIN ON LOCAL OXIDE 有权
标题翻译：当地氧化物半导体FIN
公开(公告)号：US20140061862A1
公开(公告)日：2014-03-06
申请号：US13597799
申请日：2012-08-29
申请人： Reinaldo A. VEGA , Michael V. AQUILINO , Daniel J. JAEGER
发明人： Reinaldo A. VEGA , Michael V. AQUILINO , Daniel J. JAEGER
IPC分类号： H01L29/161 , H01L21/20
CPC分类号： H01L21/76281 , H01L21/3081 , H01L21/3086 , H01L21/32 , H01L21/76208 , H01L29/66795 , H01L29/785
摘要： A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins. The first semiconductor material can be selected from materials more easily oxidized relative to the second semiconductor material to provide a uniform height for the semiconductor fins after formation of the localized oxide layer.
摘要翻译：提供了包括第一外延半导体层的半导体衬底。第一外延半导体层包括第一半导体材料，并且可以形成在下面的外延衬底层上，或者可以是整个半导体衬底。包含第二半导体材料的第二外延半导体层外延地形成在第一外延半导体层上。包括第二单晶半导体材料的部分的半导体翅片通过使用第一外延半导体层作为蚀刻停止层的第二外延半导体层图案化而形成。至少第一外延半导体层的上部被氧化以提供电绝缘半导体鳍片的局部氧化物层。第一半导体材料可以从相对于第二半导体材料更容易氧化的材料中选择，以在形成局部氧化物层之后为半导体翅片提供均匀的高度。

3. 发明申请

US20130069160A1 TRENCH ISOLATION STRUCTURE 有权
标题翻译：高分子隔离结构
公开(公告)号：US20130069160A1
公开(公告)日：2013-03-21
申请号：US13233058
申请日：2011-09-15
申请人： Michael V. AQUILINO , Reinaldo A. VEGA
发明人： Michael V. AQUILINO , Reinaldo A. VEGA
IPC分类号： H01L21/336 , H01L29/78 , B82Y40/00
CPC分类号： H01L29/66636 , H01L21/76232 , H01L21/823814 , H01L21/823878 , H01L29/1083 , H01L29/165 , H01L29/66628 , H01L29/7834 , H01L29/7846 , H01L29/7848
摘要： A trench isolation structure and method of forming the trench isolation structure are disclosed. The method includes forming a shallow trench isolation (STI) structure having an overhang and forming a gate stack. The method further includes forming source and drain recesses adjacent to the STI structure and the gate stack. The source and drain recesses are separated from the STI structure by substrate material. The method further includes forming epitaxial source and drain regions associated with the gate stack by filling the source and drain recesses with stressor material.
摘要翻译：公开了形成沟槽隔离结构的沟槽隔离结构和方法。该方法包括形成具有突出端并形成栅叠层的浅沟槽隔离（STI）结构。该方法还包括形成与STI结构和栅极堆叠相邻的源极和漏极凹部。源极和漏极凹槽通过衬底材料与STI结构分离。该方法还包括通过用应力源材料填充源极和漏极凹陷来形成与栅极堆叠相关联的外延源极和漏极区域。

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