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1. 发明授权

US09846583B2 Hardware power-on initialization of an SoC through a dedicated processor 有权
公开(公告)号：US09846583B2
公开(公告)日：2017-12-19
申请号：US14969362
申请日：2015-12-15
申请人： Xilinx, Inc.
发明人： Ahmad R. Ansari
IPC分类号： G06F15/177 , G06F9/00 , G06F9/44 , G06F11/22 , G06F11/263 , G06F15/78
CPC分类号： G06F9/4403 , G06F9/4401 , G06F11/2284 , G06F11/2635 , G06F15/781 , G06F2011/2278
摘要： In an example, a system-on-chip (SoC) includes a hardware power-on-reset (POR) sequencer circuit coupled to a POR pin. The SoC further includes a platform management unit (PMU) circuit, coupled to the hardware POR sequencer circuit, the PMU including one or more central processing units (CPUs) and a read only memory (ROM). The SoC further includes one or more processing units configured to execute a boot process. The hardware POR sequencer circuit is configured to initialize the PMU. The one or more CPUs of the PMU are configured to execute code stored in the ROM to perform a pre-boot initialization.

2. 发明授权

US12020021B2 Impactless firmware update 有权
公开(公告)号：US12020021B2
公开(公告)日：2024-06-25
申请号：US17839265
申请日：2022-06-13
申请人： XILINX, INC.
发明人： Ahmad R. Ansari , Felix Burton
IPC分类号： G06F8/656 , G06F9/4401 , G06F9/445 , G06F21/57
CPC分类号： G06F8/656 , G06F9/4401 , G06F9/445 , G06F21/572 , G06F2221/033
摘要： Techniques to update firmware without a system reset include preserving state information associated with one or more firmware services, suspending processing of firmware service requests, loading an updated firmware image, and resuming processing of firmware service requests based on the preserved state information and the updated firmware image. Unpreserved states of one or more other firmware services may be recreated upon resumption of processing of the firmware service requests.

3. 发明授权

US09495239B1 User-configurable error handling 有权
标题翻译：用户可配置的错误处理
公开(公告)号：US09495239B1
公开(公告)日：2016-11-15
申请号：US14466845
申请日：2014-08-22
申请人： Xilinx, Inc.
发明人： Sagheer Ahmad , Bradley L. Taylor , Ahmad R. Ansari , Tomai Knopp
IPC分类号： G06F11/07 , G06F11/14
CPC分类号： G06F11/0793 , G06F11/0706 , G06F11/0772 , G06F11/142 , G06F11/1441
摘要： A method for operating a programmable IC is disclosed. A set of circuits specified by a set of configuration data is operated in a set of programmable resources. In response to one of a set of status signals indicating an error, a value indicative of an error is stored in a respective one of a plurality of error status registers. The values stored in the plurality of error status registers are provided to an error handling circuit included in the set of circuits specified by the set of configuration data and operated in the programmable resources. At least one error handling process is performed by the error handling circuit as a function of values stored in the plurality of error status registers.
摘要翻译：公开了一种用于操作可编程IC的方法。由一组配置数据指定的一组电路在一组可编程资源中操作。响应于指示错误的一组状态信号中的一个，指示错误的值被存储在多个错误状态寄存器中的相应一个中。存储在多个错误状态寄存器中的值被提供给由该组配置数据指定并在可编程资源中操作的电路集合中包括的错误处理电路。由错误处理电路执行至少一个错误处理过程作为存储在多个错误状态寄存器中的值的函数。

4. 发明授权

US10789153B2 Debug controller circuit 有权
公开(公告)号：US10789153B2
公开(公告)日：2020-09-29
申请号：US15944137
申请日：2018-04-03
申请人： Xilinx, Inc.
发明人： Ahmad R. Ansari , Felix Burton , Ming-dong Chen
IPC分类号： G06F11/00 , G06F11/36 , G01R31/317 , G01R31/3185 , G06F11/22 , G06F11/267 , G06F11/273 , G06F30/34
摘要： A circuit arrangement includes one or more input buffers disposed on a system-on-chip (SoC) and configured to receive and store streaming debug packets. One or more response buffers are also disposed on the SoC. A transaction control circuit is disposed on the SoC and is configured to process each debug packet in the one or more input buffers. The processing includes decoding an operation code in the debug packet, and determining from an address in the debug packet, an interface circuit of multiple interface circuits to access a storage circuit in a subsystem of multiple sub-systems on the SoC. The processing further includes issuing a request via the interface circuit to access the storage circuit according to the operation code, and storing responses and data received from the interface circuits in the one or more response buffers.

5. 发明授权

US10067189B1 Input/output path testing and characterization using scan chains 有权
公开(公告)号：US10067189B1
公开(公告)日：2018-09-04
申请号：US15464217
申请日：2017-03-20
申请人： Xilinx, Inc.
发明人： Banadappa V. Shivaray , Ahmad R. Ansari , Sanjeeva R. Duggampudi , Pramod Surathkal , Ushasri Merugu , Bommana S. Rao , Sowmya Sheela Thati , Shashidhar S. Krishnamurthy
IPC分类号： G01R31/3185 , G01R31/3177 , G01R31/317
摘要： Disclosed circuitry includes input-output pads, receive flip-flops, and transmit flip-flops coupled to the input-output pads. Data path control circuitry is coupled to data path control flip-flops, the receive flip-flops and the transmit flip-flops. The data path control circuitry is configured to selectably couple the receive flip-flops and the transmit flip-flops to the input-output pads in response to states of the data path control flip-flops. Clock control circuitry is coupled to clock control flip-flops, the receive flip-flops and the transmit flip-flops. The clock control circuitry is configured to selectably apply one of multiple clock signals to the receive flip-flops and the transmit flip-flops in response to states of the clock control flip-flops. A first scan chain is coupled to the clock control flip-flops and the data path control flip-flops. A second scan chain is coupled to the receive flip-flops and the transmit flip-flops.

6. 发明授权

US09665509B2 Mechanism for inter-processor interrupts in a heterogeneous multiprocessor system 有权
公开(公告)号：US09665509B2
公开(公告)日：2017-05-30
申请号：US14464654
申请日：2014-08-20
申请人： Xilinx, Inc.
发明人： Ahmad R. Ansari , Felix Burton
IPC分类号： G06F13/24 , G06F9/48
CPC分类号： G06F13/24 , G06F9/4812
摘要： Apparatus and methods for handling inter-processor interrupts (IPIs) in a heterogeneous multiprocessor system are provided. The scalable IPI mechanism provided herein entails minimal logic and can be used for heterogeneous inter-processor communication, such as between application processors, real-time processors, and FPGA accelerators. This mechanism is also low cost, in terms of both logic area and programmable complexity. One example system generally includes a first processor, a second processor being of a different processor type than the first processor, and an IPI circuit. The IPI circuit typically includes a first register associated with the first processor, wherein a first bit in the first register indicates whether the first processor has requested to interrupt the second processor; and a second register associated with the second processor, wherein a second bit in the second register indicates whether the second processor has requested to interrupt the first processor.

7. 发明授权

US12056505B2 Distributed configuration of programmable devices 有权
公开(公告)号：US12056505B2
公开(公告)日：2024-08-06
申请号：US17862257
申请日：2022-07-11
申请人： XILINX, INC.
发明人： Ahmad R. Ansari , David P. Schultz
IPC分类号： G06F15/177 , G06F9/00 , G06F9/24 , G06F9/445
CPC分类号： G06F9/44505
摘要： Embodiments herein describe a distributed configuration system for a configurable device. Instead of relying solely on a central configuration manager to distribute configuration information to various subsystems in the device, the embodiments herein include configuration interface managers (CIM) that are distributed in different regions of the device, whether those regions are in one integrated circuit or include multiple integrated circuits. The embodiments can still use a central configuration manager to distribute configuration information in a device image to the plurality of CIMs, which can then forward the configuration information to their assigned regions.

8. 发明公开

US20230153156A1 SYNCHRONIZATION OF SYSTEM RESOURCES IN A MULTI-SOCKET DATA PROCESSING SYSTEM 审中-公开
公开(公告)号：US20230153156A1
公开(公告)日：2023-05-18
申请号：US17455074
申请日：2021-11-16
申请人： Xilinx, Inc.
发明人： Karthik Shankar , Jaideep Dastidar , Ahmad R. Ansari , Sagheer Ahmad
IPC分类号： G06F9/50
CPC分类号： G06F9/5027
摘要： Synchronizing system resources of a multi-socket data processing system can include providing, from a primary System-on-Chip (SOC), a trigger event to a global synchronization circuit. The primary SOC is one of a plurality of SOCS and the trigger event is provided over a first sideband channel. In response to the trigger event, the global synchronization circuit is capable of broadcasting a synchronization event to the plurality of SOCS over a second sideband channel. In response to the synchronization event, the system resource of each SOC of the plurality of SOCS is programmed with a common value. The programming synchronizes the system resources of the plurality of SOCS.

9. 发明授权

US11182110B1 On-chip memory block circuit 有权
公开(公告)号：US11182110B1
公开(公告)日：2021-11-23
申请号：US16547550
申请日：2019-08-21
申请人： Xilinx, Inc.
发明人： Ahmad R. Ansari , Sagheer Ahmad
IPC分类号： G06F3/06 , H03K19/17728 , G11C5/14 , G11C7/22 , G11C11/4076 , G06F5/06 , G06F13/16 , G06F1/3206 , G11C7/24 , H03K19/173
摘要： A memory block circuit can include a plurality of data interfaces, a switch connected to each data interface of the plurality of data interfaces, and a plurality of memory banks each coupled to the switch. Each memory bank can include a memory controller and a random access memory connected to the memory controller. The memory block circuit also includes a control interface and a management controller connected to the control interface and each memory bank of the plurality of memory banks. Each memory bank can be independently controlled by the management controller.

10. 发明授权

US10169177B1 Non-destructive online testing for safety critical applications 有权
公开(公告)号：US10169177B1
公开(公告)日：2019-01-01
申请号：US15802274
申请日：2017-11-02
申请人： Xilinx, Inc.
发明人： Banadappa V Shivaray , Pranjal Chauhan , Pramod Surathkal , Alex S. Warshofsky , Tomai Knopp , Soumitra Kumar Bhowmick , Ahmad R. Ansari
IPC分类号： G06F11/22 , G06F17/50 , H03K19/003
摘要： Embodiments herein describe a methodology for performing non-destructive LBIST when booting an integrated circuit (IC). In one embodiment, when powered on, the IC begins the boot process (e.g., a POST) which is then paused to perform LBIST. However, instead of corrupting or destroying the boot mode state of the IC, the LBIST is non-destructive. That is, after LBIST is performed, the booting process can be resumed in the same state as when LBIST began.

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