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    • 7. 发明授权
    • Sense line balancing circuit
    • 感应线平衡电路
    • US3936810A
    • 1976-02-03
    • US542395
    • 1975-01-20
    • William C. Dunn
    • William C. Dunn
    • G11C11/412G11C11/419G11C11/40
    • G11C11/412G11C11/419
    • In semiconductor memory cells of the type including flip flop circuits in each cell and two sense output lines for determining the binary bits stored in the cell, an attempt to read data stored in the cell after a previous operation, before the sense lines have been fully restored to their quiescent state can result in the loss of data. This invention provides a means for restoring the sense lines very rapidly after an operation so that loss of data is prevented and the memory may be accessed at a higher frequency.
    • 在包括每个单元中的触发器电路的类型的半导体存储器单元中,以及用于确定存储在单元中的二进制位的两个感测输出线,在感测线已经完全在前一次操作之后读取存储在该单元中的数据的尝试 恢复到静止状态可能导致数据丢失。 本发明提供了一种用于在操作之后非常快速地恢复感测线的装置,从而防止了数据的丢失并且可以以更高的频率访问存储器。