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1. 发明授权

US06614687B2 Current source component with process tracking characteristics for compact programmed Vt distribution of flash EPROM 有权
标题翻译：具有过程跟踪特性的电流源组件用于闪存EPROM的紧凑编程Vt分布
公开(公告)号：US06614687B2
公开(公告)日：2003-09-02
申请号：US09848786
申请日：2001-05-03
申请人： Ming-Shang Chen , Wenpin Lu , Baw-Chyuan Lin , Mam-Tsung Wang
发明人： Ming-Shang Chen , Wenpin Lu , Baw-Chyuan Lin , Mam-Tsung Wang
IPC分类号： G11C1134
CPC分类号： G11C16/12 , G11C11/5628 , G11C2211/565
摘要： A new structure and method with a process tracking current source component to program a flash EPROM memory is proposed. By applying a current source which varies not only with the process variation but also with the source bias of the cell being programmed, a self-convergent and high-efficiency programming can be achieved. This process tracking current source component provides less current for cells with higher erased Vt and larger current for cells with lower erased Vt. A circuit for programming a floating gate transistor includes a current source component. The current source component couples in series between the floating gate transistor and an electrical sink during a programming interval. The current source component includes an electrical characteristic substantially matching the electrical characteristic of the floating gate transistor. An integrated circuit memory module on a semiconductor substrate is disclosed. The integrated circuit memory module includes: an array of floating gate memory cells, decoders, and a plurality of current source components. The array of floating gate memory cells is arranged in M rows and N columns. The decoders couple to the M rows and N columns of memory cells to provide for reading and programming floating gate memory cells within a selected one of the M rows of the memory array. The plurality of current source components each couple in series between an electrical sink and a corresponding one of the floating gate memory cells within the selected one of the M rows during a programming interval. Each of the plurality of current source components includes an electrical characteristic substantially matching the electrical characteristic of the corresponding one of the floating gate memory cells to be programmed.
摘要翻译：提出了一种具有过程跟踪电流源组件来编程闪存EPROM存储器的新结构和方法。通过应用电流源，其不仅随工艺变化而变化，而且随着被编程的电池的源偏置而变化，可以实现自收敛和高效率的编程。该过程跟踪电流源组件为具有较高擦除Vt的电池的电池提供更少的电流，并且具有较低擦除Vt的电池的电流较小。用于编程浮动栅晶体管的电路包括电流源组件。在编程间隔期间，电流源元件串联耦合在浮栅晶体管和电汇之间。电流源组件包括基本上与浮栅晶体管的电特性匹配的电特性。公开了半导体衬底上的集成电路存储器模块。集成电路存储器模块包括：浮动栅极存储器单元，解码器和多个电流源组件的阵列。浮栅存储单元的阵列排列成M行N列。解码器耦合到存储器单元的M行和N列，以提供在存储器阵列的M行中选定的一个中的读取和编程浮动栅极存储器单元。在编程间隔期间，多个电流源分量各自串联在电汇与所选择的M行之一内的浮动栅极存储单元中的对应的一个浮动栅极存储单元之间。多个电流源组件中的每一个包括基本上匹配要编程的浮动栅极存储单元中的相应一个的电特性的电特性。

2. 发明授权

US6166955A Apparatus and method for programming of flash EPROM memory 有权
标题翻译：闪存EPROM存储器编程的装置和方法
公开(公告)号：US6166955A
公开(公告)日：2000-12-26
申请号：US350862
申请日：1999-07-09
申请人： Wenpin Lu , Ming-Shang Chen , Mam-Tsung Wang , Baw-Chyuan Lin
发明人： Wenpin Lu , Ming-Shang Chen , Mam-Tsung Wang , Baw-Chyuan Lin
IPC分类号： G11C16/04 , G11C16/12
CPC分类号： G11C16/0416 , G11C16/12
摘要： An apparatus for programming selected floating gate storage transistors in a data storage device includes a voltage supply circuit, coupled to the control gate and the source of a selected floating gate storage transistor, to supply a gate programming potential across the control gate and the source to move charge in the floating gate. Circuitry, coupled to the selected floating gate storage transistor, maintains drain current of the selected floating gate transistor at a substantially stable value during programming. In one example, the circuitry is a stable current source in parallel with a load coupled to the source of the selected floating gate transistor. The stable current source, in one embodiment, is a current mirror designed to supply a fixed current level. The load may be a resistor chosen to control a slope of a curve of source current versus source voltage such that drain current variation is limited. The load may be a diode chosen to control a slope of a curve of source current versus source voltage such that drain current variation is limited.
摘要翻译：一种用于在数据存储设备中编程所选择的浮置栅极存储晶体管的装置包括耦合到所述控制栅极和所选择的浮置栅极存储晶体管的源极的电压供应电路，以将控制栅极和源极的栅极编程电位提供给在浮动门上移动电荷。耦合到所选择的浮栅存储晶体管的电路在编程期间将所选择的浮栅晶体管的漏极电流保持在基本上稳定的值。在一个示例中，电路是与耦合到所选择的浮置栅极晶体管的源极的负载并联的稳定电流源。在一个实施例中，稳定电流源是设计成提供固定电流电平的电流镜。负载可以是被选择用于控制源电流与电源电压的曲线的斜率的电阻器，使得漏极电流变化受到限制。负载可以是被选择用于控制源电流与源电压的曲线的斜率的二极管，使得漏极电流变化受到限制。

3. 发明授权

US06363013B1 Auto-stopped page soft-programming method with voltage limited component 有权
标题翻译：具有电压限制的自动停止页面软编程方法
公开(公告)号：US06363013B1
公开(公告)日：2002-03-26
申请号：US09652230
申请日：2000-08-29
申请人： Wenpin Lu , Ying-Che Lo , Ming-Shang Chen , Baw-Chyuan Lin , Chun-Lien Su
发明人： Wenpin Lu , Ying-Che Lo , Ming-Shang Chen , Baw-Chyuan Lin , Chun-Lien Su
IPC分类号： G11C1604
CPC分类号： G11C16/12
摘要： Method for soft-programming at least one floating gate memory cell in at least one page of a persistent memory device by converging the low threshold voltages of the several cells of the page within an optimal range, and apparatus implementing the method. The methodology of the present invention teaches connecting the individual drains of the several memory cells of the device of a given page, or block, to a voltage limited constant current circuitry component. The methodology applies a first positive voltage to the word line of the page and a second positive voltage to the common source in a fixed time period to converge the pages low threshold voltage distribution. The methodology is capable of implementation on either the source or drain side of the memory array.
摘要翻译：用于通过将页面的几个单元的低阈值电压收敛在最佳范围内来软编程永久存储器件的至少一页中的至少一个浮动栅极存储单元的方法，以及实现该方法的装置。本发明的方法教导了将给定页面或块的装置的多个存储器单元的各个漏极连接到电压限制恒流电路部件。该方法在固定时间段内将第一正电压施加到页的字线和第二正电压到公共源，以使页低收集阈值电压分布。该方法能够在存储器阵列的源极或漏极侧实现。

4. 发明授权

US5912845A Method and circuit for substrate current induced hot e.sup.- injection (SCIHE) approach for V.sub.T convergence at low V.sub.CC voltage 失效
标题翻译：用于在低VCC电压下VT收敛的衬底电流感应热电子注入（SCIHE）方法和电路
公开(公告)号：US5912845A
公开(公告)日：1999-06-15
申请号：US926554
申请日：1997-09-10
申请人： Chia-Shing Chen , Mam-Tsung Wang , Wenpin Lu , Ming-Hung Chou , Ying-Che Lo , Ming-Shang Chen
发明人： Chia-Shing Chen , Mam-Tsung Wang , Wenpin Lu , Ming-Hung Chou , Ying-Che Lo , Ming-Shang Chen
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C16/107 , G11C16/3404 , G11C16/3409 , G11C16/3445
摘要： A method for soft programming memory cells and floating gate memory device. During soft programming, a gate voltage is supplied to the control gate, a drain voltage it supplied to the drain, a well voltage is supplied to the well, and an active current limiter is coupled to the source. A circuit for soft programming supplies a gate voltage to the control gate, couples a constant current source to the drain, supplies a well voltage to the well, and supplies a source voltage to the source. The gate voltage may be approximately 2 V, the drain voltage may be approximately 4 V, and the well voltage may be approximately -2 V. According to another embodiment of the invention, the gate voltage is approximately 2 V lower than the drain voltage, and the well voltage is approximately 4 V lower than the gate voltage.
摘要翻译：一种用于软编程存储单元和浮动栅极存储器件的方法。在软编程期间，向控制栅极提供栅极电压，将其提供给漏极的漏极电压，将阱电压提供给阱，并且有源限流器耦合到源极。用于软编程的电路向控制栅极提供栅极电压，将恒定电流源耦合到漏极，将阱电压提供给阱，并将源电压提供给源极。栅极电压可以为约2V，漏极电压可以为约4V，并且阱电压可以为约-2V。根据本发明的另一实施例，栅极电压比漏极电压低约2V，并且阱电压比栅极电压低约4V。

5. 发明授权

US6031766A Method and circuit for substrate current induced hot e-injection (SCIHE) approach for V.sub.T convergence at low V.sub.cc voltage 有权
标题翻译：用于在低Vcc电压下VT收敛的衬底电流感应热电子注入（SCIHE）方法和电路
公开(公告)号：US6031766A
公开(公告)日：2000-02-29
申请号：US289697
申请日：1999-04-09
申请人： Chia-Shing Chen , Mam-Tsung Wang , Wenpin Lu , Ming-Hung Chou , Ying-Che Lo , Ming-Shang Chen
发明人： Chia-Shing Chen , Mam-Tsung Wang , Wenpin Lu , Ming-Hung Chou , Ying-Che Lo , Ming-Shang Chen
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C16/107 , G11C16/3404 , G11C16/3409 , G11C16/3445
摘要： A method for soft programming memory cells and floating gate memory device. During soft programming, a gate voltage is supplied to the control gate, a drain voltage it supplied to the drain, a well voltage is supplied to the well, and an active current limiter is coupled to the source. A circuit for soft programming supplies a gate voltage to the control gate, couples a constant current source to the drain, supplies a well voltage to the well, and supplies a source voltage to the source. The gate voltage may be approximately 2 V, the drain voltage may be approximately 4 V, and the well voltage may be approximately -2 V. According to another embodiment of the invention, the gate voltage is approximately 2 V lower than the drain voltage, and the well voltage is approximately 4 V lower than the gate voltage.
摘要翻译：一种用于软编程存储单元和浮动栅极存储器件的方法。在软编程期间，向控制栅极提供栅极电压，将其提供给漏极的漏极电压，将阱电压提供给阱，并且有源限流器耦合到源极。用于软编程的电路向控制栅极提供栅极电压，将恒定电流源耦合到漏极，将阱电压提供给阱，并将源电压提供给源极。栅极电压可以为约2V，漏极电压可以为约4V，并且阱电压可以为约-2V。根据本发明的另一实施例，栅极电压比漏极电压低约2V，并且阱电压比栅极电压低约4V。

6. 发明授权

US6130452A Virtual ground flash cell with asymmetrically placed source and drain and method of fabrication 有权
标题翻译：具有不对称放置的源极和漏极的虚拟闪存单元和制造方法
公开(公告)号：US6130452A
公开(公告)日：2000-10-10
申请号：US134747
申请日：1998-08-14
申请人： Wenpin Lu , Mam-Tsung Wang
发明人： Wenpin Lu , Mam-Tsung Wang
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/7883
摘要： A memory cell having asymmetrically placed source and drain diffusions which allows programming and erasure to be obtained across one of the source or drain diffusions which extends furthest beneath the floating gate while minimizing electron tunneling at the other of the source or drain diffusions which extends only minimally beneath the floating gate. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells in which adjacent columns of cells share a single virtual ground bit-line. The method for manufacturing a memory cell having asymmetric source and drain regions and comprising the steps of: (1) forming a dielectric covering a semiconductor substrate of a first conductivity type; (2) forming a first and second column of floating gate cores on the dielectric; (3) implanting a first dopant adjacent the second column and displaced from the first column, the first dopant having a second conductivity type opposite the first conductivity type; (4) forming floating gate sidewalls in contact with the floating gate cores; (5) implanting a second dopant between the floating gate sidewalls, the second dopant having the second conductivity type; (6) forming a thermal oxide between the first and second column of floating gate cores such that oxide encroachments are formed below the floating gate cores of the first and second column and the first dopant is separated from the second column of floating gate cores by the first dielectric and the second dopant is separated from first column of the floating gate cores by the oxide encroachment; and (7) completing formation of control gate dielectric and control gates. The presence of tunneling and non-tunneling connections on the source and drain side of each cell improves the isolation between adjacent memory cells and minimizes the disturb problem.
摘要翻译：具有不对称放置的源极和漏极扩散的存储单元，其允许在源极或漏极扩散之间获得编程和擦除，该扩散最远在浮置栅极下方延伸，同时最小化源极或漏极扩散的另一个处的电子隧穿，在浮动门下面。一种非易失性半导体存储器件，包括单元的行和列布置，其中相邻列的单元共享单个虚拟接地位线。一种制造具有不对称源区和漏区的存储单元的方法，包括以下步骤：（1）形成覆盖第一导电类型的半导体衬底的电介质; （2）在电介质上形成第一和第二列浮栅; （3）在第二列附近注入第一掺杂物并从第一列移位，第一掺杂剂具有与第一导电类型相反的第二导电类型; （4）形成与浮动栅芯接触的浮动栅极侧壁; （5）在所述浮置栅极侧壁之间注入第二掺杂剂，所述第二掺杂物具有所述第二导电类型; （6）在第一和第二列的浮栅之间形成热氧化物，使得在第一和第二列的浮置栅芯之下形成氧化物侵蚀，并且第一掺杂剂通过第一电介质和第二掺杂剂通过氧化物侵蚀与浮栅的第一列分离; 和（7）完成控制栅介质和控制栅的形成。在每个单元的源极和漏极侧存在隧道和非隧道连接改善了相邻存储单元之间的隔离，并使干扰问题最小化。

7. 发明授权

US6055190A Device and method for suppressing bit line column leakage during erase verification of a memory cell 有权
标题翻译：用于在存储器单元的擦除验证期间抑制位线列泄漏的装置和方法
公开(公告)号：US6055190A
公开(公告)日：2000-04-25
申请号：US268557
申请日：1999-03-15
申请人： Wenpin Lu , Ying-Che Lo , Ming-Jye Chiou , Mam-Tsung Wang
发明人： Wenpin Lu , Ying-Che Lo , Ming-Jye Chiou , Mam-Tsung Wang
IPC分类号： G11C16/34 , G11C16/06
CPC分类号： G11C16/3445 , G11C16/344
摘要： A device and method of operation for an improved erase-verify device in which the non-selected cells, within a bit line column of an array of cells, remain inactive. Only the active cell is verified with minimum bit line column leakage associated with the operation of erase verification. Erase verification for a memory array is achieved by applying a source voltage (generally positive) to the common source line associated with a column of cells in the array. This will raise the threshold voltages of the cells (through the body effect of the semiconductor device) to a level higher than the predetermined minimum erased threshold voltage. The non-selected wordlines are coupled to a reference level below the threshold level of the cell (e.g. ground), and the selected wordline is coupled to a positive voltage which is a function of the source voltage. The source voltage is also added to the drain source voltage. The source voltage thereby serves as a feedback input to both the wordline and bit line inputs. Thereafter, a fixed drain-to-source bias is applied to the selected bit line column to conduct current for verification of the cell. The source voltage feedback allows the wordline voltage to be adjusted so that read current through the selected cell can be maintained at a desired level. Using this approach, the bit line column leakage caused by over-erased cells can be effectively suppressed, and an accurate verification result can be achieved.
摘要翻译：一种用于改进的擦除验证装置的装置和操作方法，其中在单元阵列的位线列内的未选择的单元保持不活动。只有活动单元格被验证与擦除验证的操作相关联的最小位线列泄漏。对存储器阵列的擦除验证是通过将源电压（通常为正）施加到与阵列中的一列单元相关联的公共源极线来实现的。这将使电池的阈值电压（通过半导体器件的本体效应）升高到高于预定的最小擦除阈值电压的电平。未选择的字线被耦合到低于单元的阈值电平（例如接地）的参考电平，并且所选择的字线耦合到作为源电压的函数的正电压。源极电压也被加到漏源电压上。因此，源电压用作对字线和位线输入的反馈输入。此后，将固定的漏极 - 源极偏压施加到所选择的位线列，以传导电流以验证电池。源电压反馈允许调节字线电压，使得通过所选择的单元的读取电流可以保持在期望的水平。利用这种方法，可以有效地抑制由过度擦除的单元引起的位线列泄漏，并且可以实现准确的验证结果。

8. 发明授权

US5963808A Method of forming an asymmetric bird's beak cell for a flash EEPROM 失效
标题翻译：形成快闪EEPROM的不对称鸟嘴单元的方法
公开(公告)号：US5963808A
公开(公告)日：1999-10-05
申请号：US783995
申请日：1997-01-15
申请人： Wenpin Lu , Tao-Cheng Lu , Mam-Tsung Wang
发明人： Wenpin Lu , Tao-Cheng Lu , Mam-Tsung Wang
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/7883
摘要： A memory cell having an asymmetric source and drain connection to buried bit-lines providing a Fowler-Nordheim tunneling region and a non-tunneling region defined by a bird's beak encroachment on each of the cells. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells in which adjacent columns of cells share a single bit-line. The method for manufacturing a memory cell having asymmetric source and drain regions and comprising the steps of: (1) forming a dielectric covering a semiconductor substrate of a first conductivity type; (2) forming a column of floating gates on the dielectric; (3) forming an inhibit mask adjacent a first side of the column of floating gates; (4) implanting a dopant adjacent the first side and a second side of the column of floating gates, the first dopant having a second conductivity type opposite the first conductivity type; (5) forming a thermal oxide adjacent the first and second side of the column of floating gates such that the dopant adjacent the first side of the column is separated from the floating gates by the dielectric and the dopant adjacent the second side of the column is separated from the floating gates by a bird's beak encroachment of the thermal oxide formation; and (6) completing formation of control gate dielectric and control gates.
摘要翻译：具有不对称的源极和漏极连接到具有Fowler-Nordheim隧道区域的掩埋位线的存储单元以及由每个单元上的鸟喙侵入限定的非隧穿区域。一种非易失性半导体存储器件，包括单元的行和列排列，其中相邻列的单元共享单个位线。一种制造具有不对称源区和漏区的存储单元的方法，包括以下步骤：（1）形成覆盖第一导电类型的半导体衬底的电介质; （2）在电介质上形成一列浮栅; （3）在所述浮栅的所述列的第一侧附近形成抑制掩模; （4）在所述浮栅的所述第一侧和所述第二侧附近注入掺杂剂，所述第一掺杂剂具有与所述第一导电类型相反的第二导电类型; （5）在浮置栅极列的第一和第二侧附近形成热氧化物，使得邻近该列的第一侧的掺杂剂通过电介质离开浮动栅极并且邻近该第二侧的掺杂剂是通过鸟喙侵蚀热氧化物形成与浮动门分离; （6）完成控制栅介质和控制栅的形成。

9. 发明授权

US5837584A Virtual ground flash cell with asymmetrically placed source and drain and method of fabrication 失效
标题翻译：具有不对称放置的源极和漏极的虚拟闪存单元和制造方法
公开(公告)号：US5837584A
公开(公告)日：1998-11-17
申请号：US783994
申请日：1997-01-15
申请人： Wenpin Lu , Mam-Tsung Wang
发明人： Wenpin Lu , Mam-Tsung Wang
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/7883
摘要： A memory cell having asymmetrically placed source and drain diffusions which allows programming and erasure to be obtained across one of the source or drain diffusions which extends furthest beneath the floating gate while minimizing electron tunneling at the other of the source or drain diffusions which extends only minimally beneath the floating gate. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells in which adjacent columns of cells share a single virtual ground bit-line. The method for manufacturing a memory cell having asymmetric source and drain regions and comprising the steps of (1) forming a dielectric covering a semiconductor substrate of a first conductivity type; (2) forming a first and second column of floating gate cores on the dielectric; (3) implanting a first dopant adjacent the second column and displaced from the first column, the first dopant having a second conductivity type opposite the first conductivity type; (4) forming floating gate sidewalls in contact with the floating gate cores; (5) implanting a second dopant between the floating gate sidewalls, the second dopant having the second conductivity type; (6) forming a thermal oxide between the first and second column of floating gate cores such that oxide encroachments are formed below the floating gate cores of the first and second column and the first dopant is separated from the second column of floating gate cores by the first dielectric and the second dopant is separated from first column of the floating gate cores by the oxide encroachment; and (7) completing formation of control gate dielectric and control gates. The presence of tunneling and non-tunneling connections on the source and drain side of each cell improves the isolation between adjacent memory cells and minimizes the disturb problem.
摘要翻译：具有不对称放置的源极和漏极扩散的存储单元，其允许在源极或漏极扩散之间获得编程和擦除，该扩散最远在浮置栅极下方延伸，同时最小化源极或漏极扩散的另一个处的电子隧穿，在浮动门下面。一种非易失性半导体存储器件，包括单元的行和列布置，其中相邻列的单元共享单个虚拟接地位线。一种用于制造具有不对称源区和漏区的存储单元的方法，包括以下步骤：（1）形成覆盖第一导电类型的半导体衬底的电介质; （2）在电介质上形成第一和第二列浮栅; （3）在第二列附近注入第一掺杂物并从第一列移位，第一掺杂剂具有与第一导电类型相反的第二导电类型; （4）形成与浮动栅芯接触的浮动栅极侧壁; （5）在所述浮置栅极侧壁之间注入第二掺杂剂，所述第二掺杂物具有所述第二导电类型; （6）在第一和第二列的浮栅之间形成热氧化物，使得在第一和第二列的浮置栅芯之下形成氧化物侵蚀，并且第一掺杂剂通过第一电介质和第二掺杂剂通过氧化物侵蚀与浮栅的第一列分离; 和（7）完成控制栅介质和控制栅的形成。在每个单元的源极和漏极侧存在隧道和非隧道连接改善了相邻存储单元之间的隔离，并使干扰问题最小化。

10. 发明授权

US07971177B2 Design tool for charge trapping memory using simulated programming operations 有权
标题翻译：使用模拟编程操作的电荷捕获存储器的设计工具
公开(公告)号：US07971177B2
公开(公告)日：2011-06-28
申请号：US12182352
申请日：2008-07-30
申请人： Shaw Hung Ku , Chia Wei Wu , Ming Shang Chen , Wenpin Lu
发明人： Shaw Hung Ku , Chia Wei Wu , Ming Shang Chen , Wenpin Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5018 , G06F17/5036 , G06F2217/10 , G06F2217/78
摘要： A method for simulating operation of a charge trapping memory cell which computes the amount of charge trapped by determining first tunneling current through the tunneling layer, determining second tunneling current out of the charge trapping layer to the gate, determining third tunneling current escaping from traps in the charge trapping layer and tunneling out to the gate, and integrating said tunneling currents over a time interval. A change in threshold voltage can be computed for a transistor including the charge trapping structure. The parameter set can include only physical parameters, including layer thickness, band offsets and dielectric constants.
摘要翻译：一种用于模拟电荷捕获存储单元的操作的方法，所述电荷捕获存储单元通过确定通过所述隧道层的第一隧道电流来计算所捕获的电荷量，确定从所述电荷俘获层到所述栅极的第二隧穿电流，确定从陷阱中逃逸的第三隧穿电流电荷捕获层并隧穿到栅极，并在一段时间间隔内积分所述隧穿电流。可以对包括电荷捕获结构的晶体管计算阈值电压的变化。参数集可以仅包括物理参数，包括层厚度，带偏移和介电常数。

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