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1. 发明授权

US4393476A Random access memory dual word line recovery circuitry 失效
标题翻译：随机存取存储器双字线恢复电路
公开(公告)号：US4393476A
公开(公告)日：1983-07-12
申请号：US282767
申请日：1981-07-13
申请人： Warren R. Ong
发明人： Warren R. Ong
IPC分类号： G11C11/414 , G11C8/08 , G11C11/413 , G11C11/40
CPC分类号： G11C11/413 , G11C8/08
摘要： A discharge circuit for rapidly discharging the word lines of random access memories to thereby prevent erroneous reading from or writing into the memory during periods when the word lines are in a mid-state transition between selected and deselected voltage levels. Each discharge circuit associated with the memory word lines includes a transistor that is conductive only when a full select voltage level is applied to the word line and which controls conduction of a second multi-collector transistor coupled between top and bottom lines of a word line pair and a current source to discharge the word line pair during the mid-state transition period and to thus increase the speed capabilities of the memory.
摘要翻译：一种放电电路，用于快速放电随机存取存储器的字线，从而防止在字线处于选择电压和取消选择的电压电平之间的中间状态转换期间的错误读取或写入存储器。与存储字线相关联的每个放电电路包括只有当全选择电压电平施加到字线并且控制耦合在字线对的顶线和底线之间的第二多集电极晶体管的导通时才导通的晶体管以及在中间状态转换期间放电字线对的电流源，从而提高存储器的速度能力。

2. 发明授权

US4386420A Dynamic read reference voltage generator 失效
标题翻译：动态读取参考电压发生器
公开(公告)号：US4386420A
公开(公告)日：1983-05-31
申请号：US313001
申请日：1981-10-19
申请人： Warren R. Ong
发明人： Warren R. Ong
IPC分类号： G11C7/14 , G11C11/416 , G11C7/00
CPC分类号： G11C11/416 , G11C7/14
摘要： A method and circuitry (5) for enhancing the reproducibility and reliability of circuitry for reading a memory array (10a, 10b, 10a', 10b') provides a dynamically generated reference voltage for the sensing circuitry. The invention senses the highest word line voltage and communicates a voltage derived therefrom to the sensing circuitry (26, 27, 28, 29; 26', 27', 28', 29'; 32, 33) to provide a reference voltage. A voltage clamp (62) is coupled to the circuitry for communicating the highest word line voltage (50) to prevent the reference voltge from following the word line too low during transitions. The invention is rendered compatible with the existing write circuitry associated with the memory array (10a, 10b, 10a', 10b') by the provision of disabling circuitry (65) coupled to the communicating circuitry (55, 57) and to the clamp (62). The disabling circuitry (65) is responsive to a write control signal and operates to prevent the high word line voltage from being communicated to the sensing circuitry, and further operates to allow the communication of lower voltage than would normally be permitted by the clamp (62).
摘要翻译：用于增强用于读取存储器阵列（10a，10b，10a'，10b'）的电路的再现性和可靠性的方法和电路（5）为感测电路提供动态产生的参考电压。本发明感测到最高的字线电压，并将从其导出的电压传送到感测电路（26,27,28,29; 26'，27'，28'，29'; 32,33）以提供参考电压。电压钳位器（62）耦合到用于传送最高字线电压（50）的电路，以防止在转换期间参考电压跟随字线太低。本发明通过提供耦合到通信电路（55,57）和钳位电路（55,57）的禁用电路（65）与现有的与存储器阵列（10a，10b，10a'，10b'）相关联的写入电路 62）。禁用电路（65）响应于写入控制信号并且操作以防止高字线电压被传送到感测电路，并且还进一步操作以允许比通常由钳位（62）允许的更低的电压通信）。

3. 发明授权

US4198698A Chip select power-down control circuitry 失效
标题翻译：芯片选择掉电控制电路
公开(公告)号：US4198698A
公开(公告)日：1980-04-15
申请号：US966985
申请日：1978-12-06
申请人： Warren R. Ong , Walford Ho
发明人： Warren R. Ong , Walford Ho
IPC分类号： G11C5/14 , G11C7/02 , G11C11/4067 , G11C11/414
CPC分类号： G11C5/14 , G11C11/4067 , G11C11/414 , Y10T307/826
摘要： Circuitry responsive to a memory chip de-select signal for very rapidly decoupling the memory from its peripheral circuits and for turning off all unnecessary power and, upon occurrence of a chip select signal, for rapidly restoring power and then recoupling the memory after a preselected word line voltage is reached and all transients have subsided, thereby preventing erroneous writing and reading during chip select and de-select.
摘要翻译：响应于存储器芯片解除选择信号的电路非常快速地将存储器与其外围电路解耦并且用于关闭所有不必要的电力，并且在发生芯片选择信号时，用于快速恢复功率，然后在预选字之后重新耦合存储器线电压达到并且所有瞬变已经消退，从而防止芯片选择和取消选择期间错误的写入和读取。

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