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1. 发明申请

US20190045031A1 LOW-LATENCY LINK COMPRESSION SCHEMES 审中-公开
公开(公告)号：US20190045031A1
公开(公告)日：2019-02-07
申请号：US16014690
申请日：2018-06-21
申请人： Wajdi Feghali , Vinodh Gopal , Kirk Yap , Sean Gulley , Simon Peffers
发明人： Wajdi Feghali , Vinodh Gopal , Kirk Yap , Sean Gulley , Simon Peffers
IPC分类号： H04L29/06 , H04L12/863
摘要： Methods and apparatus for low-latency link compression schemes. Under the schemes, selected packets or messages are dynamically selected for compression in view of current transmit queue levels. The latency incurred during compression and decompression is not added to the data-path, but sits on the side of the transmit queue. The system monitors the queue depth and, accordingly, initiates compression jobs based on the depth. Different compression levels may be dynamically selected and used based on queue depth. Under various schemes, either packets or messages are enqueued in the transmit queue or pointers to such packets and messages are enqueued. Additionally, packets/message may be compressed prior to being enqueued, or after being enqueued, wherein an original uncompressed packet is replaced with a compressed packet. Compressed and uncompressed packets may be stored in queues or buffers and transmitted using a different numbers of transmit cycles based on their compression ratios. The schemes may be implemented to improve the effective bandwidth of various types of links, including serial links, bus-type links, and socket-to-socket links in multi-socket systems.

2. 发明申请

US20100205455A1 DIFFUSION AND CRYPTOGRAPHIC-RELATED OPERATIONS 有权
标题翻译：扩展和与CRIPTO图相关的操作
公开(公告)号：US20100205455A1
公开(公告)日：2010-08-12
申请号：US12368196
申请日：2009-02-09
申请人： Vinodh Gopal , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Robert Ottavi , Sean Gulley
发明人： Vinodh Gopal , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Robert Ottavi , Sean Gulley
IPC分类号： H04L9/00
CPC分类号： G09C1/00 , H04L9/0637 , H04L2209/12
摘要： An embodiment includes at least one processing unit to perform at least first and second sets of diffusion-related operations to produce a resulting block from a data block, and that includes at least one stage and at least one other stage. The at least one stage is to select one of first operands and second operands input to the at least one other stage. The first and second operands are respectively associated with the first and second sets of operations, respectively. The at least one other stage involves arithmetic and logical operations common to both the first and second sets of operations. At least one other processing unit is to perform at least one set of cryptographic-related operations (different, at least in part, from the first and second sets of operations) on at least one of (1) another block to produce the data block and (2) the resulting block.
摘要翻译：一个实施例包括至少一个处理单元，用于执行至少第一和第二组扩散相关操作以从数据块产生结果块，并且其包括至少一个阶段和至少一个其他阶段。所述至少一个级是选择输入至少一个其他级的第一操作数和第二操作数之一。第一和第二操作数分别分别与第一和第二组操作相关联。所述至少一个其他阶段涉及对于第一和第二组操作共同的算术和逻辑运算。至少一个其他处理单元将在（1）另一个块中的至少一个上执行至少一组密码相关操作（至少部分地不同于第一和第二组操作），以产生数据块和（2）得到的块。

3. 发明授权

US08363828B2 Diffusion and cryptographic-related operations 有权
标题翻译：扩散和加密相关操作
公开(公告)号：US08363828B2
公开(公告)日：2013-01-29
申请号：US12368196
申请日：2009-02-09
申请人： Vinodh Gopal , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Robert Ottavi , Sean Gulley
发明人： Vinodh Gopal , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Robert Ottavi , Sean Gulley
IPC分类号： G06F21/00
CPC分类号： G09C1/00 , H04L9/0637 , H04L2209/12
摘要： An embodiment includes at least one processing unit to perform at least first and second sets of diffusion-related operations to produce a resulting block from a data block, and that includes at least one stage and at least one other stage. The at least one stage is to select one of first operands and second operands input to the at least one other stage. The first and second operands are respectively associated with the first and second sets of operations, respectively. The at least one other stage involves arithmetic and logical operations common to both the first and second sets of operations. At least one other processing unit is to perform at least one set of cryptographic-related operations (different, at least in part, from the first and second sets of operations) on at least one of (1) another block to produce the data block and (2) the resulting block.
摘要翻译：一个实施例包括至少一个处理单元，用于执行至少第一和第二组扩散相关操作以从数据块产生结果块，并且其包括至少一个阶段和至少一个其他阶段。所述至少一个级是选择输入至少一个其他级的第一操作数和第二操作数之一。第一和第二操作数分别分别与第一和第二组操作相关联。所述至少一个其他阶段涉及对于第一和第二组操作共同的算术和逻辑运算。至少一个其他处理单元将在（1）另一个块中的至少一个上执行至少一组密码相关操作（至少部分地不同于第一和第二组操作），以产生数据块和（2）得到的块。

4. 发明申请

US20160191238A1 SMS4 ACCELERATION HARDWARE 有权
标题翻译： SMS4加速硬件
公开(公告)号：US20160191238A1
公开(公告)日：2016-06-30
申请号：US14582707
申请日：2014-12-24
申请人： Kirk YAP , Gilbert Wolrich , Sudhir Satpathy , Sean Gulley , Vinodh Gopal , Sanu Mathew , Wajdi Feghali
发明人： Kirk YAP , Gilbert Wolrich , Sudhir Satpathy , Sean Gulley , Vinodh Gopal , Sanu Mathew , Wajdi Feghali
IPC分类号： H04L9/08
CPC分类号： H04L9/0822 , G09C1/00 , H04L9/0631 , H04L2209/122
摘要： Embodiments of an invention for SMS4 acceleration hardware are disclosed. In an embodiment, an apparatus includes SMS4 hardware and key transformation hardware. The SMS4 hardware is to execute a round of encryption and a round of key expansion. The key transformation hardware is to transform a key to provide for the SMS4 hardware to execute a round of decryption.
摘要翻译：公开了用于SMS4加速硬件的发明的实施例。在一个实施例中，一种装置包括SMS4硬件和密钥变换硬件。 SMS4硬件是执行一轮加密和一轮关键扩展。密钥转换硬件是转换密钥以提供SMS4硬件来执行一轮解密。

5. 发明申请

US20190042496A1 DELAYED LINK COMPRESSION SCHEME 审中-公开
公开(公告)号：US20190042496A1
公开(公告)日：2019-02-07
申请号：US16140472
申请日：2018-09-24
申请人： Simon N. Peffers , Kirk S. Yap , Sean Gulley , Vinodh Gopal , Wajdi Feghali
发明人： Simon N. Peffers , Kirk S. Yap , Sean Gulley , Vinodh Gopal , Wajdi Feghali
IPC分类号： G06F13/16 , H04L29/06 , G06F13/28 , G06F13/40
摘要： Apparatus, systems and methods for implementing delayed decompression schemes. As a burst of packets comprising compressed packets and uncompressed packets are received over an interconnect link, they are buffered in a receive buffer without decompression. Subsequently, the packets are forwarded from the receive buffer to a consumer such as processor core, with the compressed packets being decompressed prior to reaching the processor core. Under a first delayed decompression approach, packets are decompressed when they are read from the receive buffer in conjunction with forwarding the uncompressed packet (or uncompressed data contained therein) to the consumer. Under a second delayed decompression scheme, the packets are read from the receive buffer and forwarded to a decompressor using a first datapath width matching the width of the packets, decompressed, and then forwarded to the consumer using a second datapath width matching the width of the uncompressed data.

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