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1. 发明申请

US20070242756A1 Data-modulating apparatus, data-modulating method, data-demodulating apparatus, data-demodulating method, and data-providing medium 失效
标题翻译：数据调制装置，数据调制方式，数据解调装置，数据解调方式以及数据提供媒体
公开(公告)号：US20070242756A1
公开(公告)日：2007-10-18
申请号：US11811023
申请日：2007-06-08
申请人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
发明人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
IPC分类号： H04B14/04
CPC分类号： G11B20/1426 , G11B20/1403 , G11B2020/1287 , G11B2020/1453 , G11B2020/1457 , H03M5/145 , H04L7/0083 , H04L7/041 , H04L7/044
摘要： A SYNC bit inserting section 14 adds a sync signal to a train of codes, after adding a minimum run, said sync signal having a pattern that breaks a maximum run. It is thereby possible to provide a reliable sync signal pattern.
摘要翻译： SYNC位插入部分14在添加最小运行之后将同步信号添加到一串代码，所述同步信号具有中断最大运行的模式。从而可以提供可靠的同步信号模式。

2. 发明授权

US5537422A Synchronization signal detector, synchronization signal detecting method and demodulator 失效
标题翻译：同步信号检测器，同步信号检测方法和解调器
公开(公告)号：US5537422A
公开(公告)日：1996-07-16
申请号：US565620
申请日：1995-11-22
申请人： Yoshihide Shimpuku , Hiroyuki Ino , Yasuyuki Chaki , Toshiyuki Nakagawa
发明人： Yoshihide Shimpuku , Hiroyuki Ino , Yasuyuki Chaki , Toshiyuki Nakagawa
IPC分类号： G11B20/12 , G11B20/14 , G11B27/30 , H03M5/06 , H03M7/14 , H03M7/40 , H03M13/00
CPC分类号： G11B20/1403 , G11B20/1426 , G11B27/3027 , G11B20/1217 , G11B2220/2545
摘要： A synchronization detector includes a NRZI circuit for extracting edge portions of RF signals detected as binary-valued signals to form a pulse train, a counter for counting the number of channel clocks in the distance between transitions represented by the edge portions, a latch circuit operated responsive to pulses from the NRZI circuit for holding a number of previously counted channel clocks immediately preceding a current count of channel clocks, and AND gates and an OR gate for detecting synchronization signals when the combination of the channel clocks from the counter and the latch circuit is the combination of the maximum distance between transitions Tmax and Tmax-kT (k=1 or 2) of a (d, k; m, n; r) modulation code. Synchronization signals may be detected promptly even if the frame structure is increased in size to enable restoration of synchronization to be expedited when frame structure synchronization is not in order. A demodulator utilizing the synchronization signal detector is also disclosed.
摘要翻译：同步检测器包括：NRZI电路，用于提取被检测为二进制值信号的RF信号的边缘部分以形成脉冲序列;计数器，用于计数由边缘部分表示的跃迁之间的距离的信道时钟数;锁存电路，响应于来自NRZI电路的脉冲，用于保持紧邻当前通道时钟计数之前的多个先前计数的通道时钟;以及与门和用于检测同步信号的或门，当来自计数器和锁存电路的通道时钟的组合是（d，k; m，n; r）调制码的转换Tmax和Tmax-kT（k = 1或2）之间的最大距离的组合。即使框架结构的大小增加，也可以及时检测同步信号，以便在帧结构同步不顺序时能够恢复同步。还公开了利用同步信号检测器的解调器。

3. 发明申请

US20070014370A1 Method and apparatus for modulating and demodulating data into a variable length code and a providing medium for implementing the method 有权
公开(公告)号：US20070014370A1
公开(公告)日：2007-01-18
申请号：US11525484
申请日：2006-09-22
申请人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
发明人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
IPC分类号： H04B14/04
CPC分类号： G11B20/1426 , G11B20/1403 , G11B2020/1287 , G11B2020/1453 , G11B2020/1457 , H03M5/145 , H04L7/0083 , H04L7/041 , H04L7/044
摘要： A SYNC bit inserting section 14 adds a sync signal to a train of codes, after adding a minimum run, said sync signal having a pattern that breaks a maximum run. It is thereby possible to provide a reliable sync signal pattern.

4. 发明申请

US20050190084A1 Method and apparatus for modulating and demodulating data into a variable length code and a providing medium for implementing the method 有权
公开(公告)号：US20050190084A1
公开(公告)日：2005-09-01
申请号：US11088712
申请日：2005-03-24
申请人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
发明人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
IPC分类号： H03M7/14 , G11B20/14 , H03M5/14 , H04L7/00 , H04L7/04 , H03M7/00
CPC分类号： G11B20/1426 , G11B20/1403 , G11B2020/1287 , G11B2020/1453 , G11B2020/1457 , H03M5/145 , H04L7/0083 , H04L7/041 , H04L7/044
摘要： A SYNC bit inserting section 14 adds a sync signal to a train of codes, after adding a minimum run, said sync signal having a pattern that breaks a maximum run. It is thereby possible to provide a reliable sync signal pattern.

5. 发明申请

US20050156760A1 Data-modulating apparatus, data-modulating method, data-demodulating apparatus, data-demodulating method, and data-providing medium 有权
标题翻译：数据调制装置，数据调制方式，数据解调装置，数据解调方式以及数据提供媒体
公开(公告)号：US20050156760A1
公开(公告)日：2005-07-21
申请号：US11078129
申请日：2005-03-10
申请人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
发明人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
IPC分类号： H03M7/14 , G11B20/14 , H03M5/14 , H04L7/00 , H04L7/04 , H03M7/00 , H03M7/40
CPC分类号： G11B20/1426 , G11B20/1403 , G11B2020/1287 , G11B2020/1453 , G11B2020/1457 , H03M5/145 , H04L7/0083 , H04L7/041 , H04L7/044
摘要： A SYNC bit inserting section 14 adds a sync signal to a train of codes, after adding a mniininum run, said sync signal having a pattern that breaks a maximum run. It is thereby possible to provide a reliable sync signal pattern.
摘要翻译： SYNC位插入部分14在添加了mniininum运行之后，将一个同步信号添加到一列代码，所述同步信号具有中断最大运行的模式。从而可以提供可靠的同步信号模式。

6. 发明授权

US06175318B1 Device for encoding/decoding n-bit source words into corresponding m-bit channel words, and vice versa 失效
标题翻译：将n位源字编码/解码为相应的m位通道字的装置，反之亦然
公开(公告)号：US06175318B1
公开(公告)日：2001-01-16
申请号：US09217427
申请日：1998-12-21
申请人： Josephus A. H. M. Kahlman , Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara , Kousuke Nakamura
发明人： Josephus A. H. M. Kahlman , Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara , Kousuke Nakamura
IPC分类号： H03M700
CPC分类号： G11B20/1426 , H03M5/145
摘要： An encoder for encoding a stream of data bits of a binary source signal into a stream of data bits of a binary channel signal, the bitstream of the source signal being divided into smaller n-bit source words (x1, x2) which are converted by a logic circuit converter in the encoder into corresponding m-bit channel words, (y1, y2, y3). The conversion of each n-bit source word is parity preserving (see Table I and FIG. 1). The relations hold that m>n≧1, p≧1, and p can vary. Preferably, m=n+1. In order to comply with (d, k) runlength requirements, certain blocks of 2-bit source words are encoded into particular blocks of 3-bit channel words. A decoder is also disclosed for decoding a channel signal produced by the encoder.
摘要翻译：一种编码器，用于将二进制源信号的数据比特流编码为二进制信道信号的数据比特流，源信号的比特流被分成较小的n比特源字（x1，x2），其被转换为将编码器中的逻辑电路转换器转换成相应的m位通道字，（y1，y2，y3）。每个n位源字的转换是奇偶校验（见表1和图1）。关系认为m> n> = 1，p> = 1，p可以变化。优选地，m = n + 1。为了符合（d，k）游程长度要求，2位源字的某些块被编码成3位通道字的特定块。还公开了一种用于对由编码器产生的信道信号进行解码的解码器。

7. 发明授权

US5600315A Modulating method and demodulating apparatus 失效
标题翻译：调制方式及解调装置
公开(公告)号：US5600315A
公开(公告)日：1997-02-04
申请号：US245360
申请日：1994-05-18
申请人： Yoshihide Shimpuku , Toshiyuki Nakagawa
发明人： Yoshihide Shimpuku , Toshiyuki Nakagawa
IPC分类号： G11B20/14 , H03M5/14 , H03M7/14 , H03M7/00
CPC分类号： G11B20/1426 , H03M5/145 , G11B2020/1461
摘要： A modulation apparatus for converting digital data having the basic data length equal to m bits into a variable length code (d, k; m, n; r) having the basic codeword length of n bits is disclosed. The apparatus includes an encoder 12 for determining the constraint length i of data supplied from a shift register 11, based upon m bits as a unit, a selector 13, plural conversion tables 14.sub.1 and an unfixed bit processing circuit 16.sub.1. The selector 13 selects one of the conversion tables 14.sub.1 based upon the constraint length i and transmits m.times.i bit data to the selected conversion table 14.sub.1, which then converts the m.times.i bit data into n.times.i bit codewords. The unfixed bit processing circuit 16.sub.1 sets a bit at a preset position of a codeword among the codewords which gives an infinite value of the maximum run, or a bit at a preset position of a codeword among the codewords which has the maximum number of consecutive "0"s from the least significant bit towards upper order side bits, as being an unfixed bit, and sets the unfixed bit to "1" if d or more "0"s are consecutive to the unfixed bit. With the present modulation apparatus, the minimum length between transitions T.sub.min may be enlarged as compared to that in EFM for increasing the recording density, while the maximum length of transitions T.sub.max may also be increased as compared to that for VFM.
摘要翻译：一种调制装置，用于将基本数据长度等于+ E的数字数据，uns m + EE位转换为具有+ E的基本码字长度的可变长度码（d，k; m，n; r），uns + EE位被公开。该装置包括编码器12，用于基于+ E，uns m + EE位作为单位确定从移位寄存器11提供的数据的约束长度+ E，uns i + EE，选择器13，多个转换表141和非固定位处理电路161.选择器13基于约束长度+ E，uns i + EE选择转换表141之一，并将mxi位数据发送到所选择的转换表141，转换表141将mxi位数据转换为nxi 位代码字。不固定位处理电路161将给出无限值最大值的码字中的码字的预设位置或具有连续“最大值”的最大数量的码字中的码字的预定位置的比特设置为“ 如果+ E，uns d + EE或更多的“0”连续到未固定的位，则从最低有效位到高阶位的0作为不固定位，并将未固定位设置为“1”。使用本调制装置，与用于增加记录密度的EFM相比，转换Tmin之间的最小长度可以被扩大，而与VFM相比，转换Tmax的最大长度也可以增加。

8. 发明授权

US5432799A Modulating method 失效
标题翻译：调制方式
公开(公告)号：US5432799A
公开(公告)日：1995-07-11
申请号：US64764
申请日：1993-05-19
申请人： Yoshihide Shimpuku , Hiroyuki Ino , Yasuyuki Chaki , Toshiyuki Nakagawa
发明人： Yoshihide Shimpuku , Hiroyuki Ino , Yasuyuki Chaki , Toshiyuki Nakagawa
IPC分类号： G11B7/00 , G11B7/004 , G11B7/0045 , G11B20/14 , H03M7/46 , H03M13/00
CPC分类号： G11B20/1426
摘要： A method of modulating digital data to a variable-length code having parameters d, k, m, n, and r for recording information on and reproducing the same from an optical disc. The optimal range of a minimum run length d corresponding to the minimum number of successive same symbols is determined by a procedure which includes a first step to determine the minimum S/N required for obtaining a desired error rate from the relationship between a bit error rate and the S/N when d=0; a second step to obtain the relationship between a change of the numerical value d and that of the S/N by calculating, on the basis of the required minimum S/N obtained at the first step, the S/N loss caused due to the change of the numerical value d; and a third step to determine, from the relationship between the numerical value d and the S/N, the range of the value d corresponding to the S/N of the transmission characteristic dependent on an optical system and an optical disc.
摘要翻译：将数字数据调制为具有参数d，k，m，n和r的可变长度代码的方法，用于从光盘记录信息并从光盘再现信息。对应于连续相同符号的最小数量的最小游程长度d的最佳范围由包括第一步骤的步骤来确定，该步骤确定从误码率之间的关系中获得期望误码率所需的最小S / N 当d = 0时S / N; 通过基于在第一步骤中获得的所需最小S / N计算由于第一步骤所产生的S / N损失而获得数值d与S / N的变化之间的关系的第二步骤数值变化d; 以及第三步骤，根据数值d和S / N之间的关系，确定与取决于光学系统和光盘的传输特性的S / N相对应的值d的范围。

9. 发明授权

US5355133A Data modulating method and apparatus and data demodulating method and apparatus 失效
标题翻译：数据调制方法及装置及数据解调方法及装置
公开(公告)号：US5355133A
公开(公告)日：1994-10-11
申请号：US15477
申请日：1993-02-09
申请人： Yoshihide Shimpuku , Hiroyuki Ino , Yasuyuki Chaki , Toshiyuki Nakagawa
发明人： Yoshihide Shimpuku , Hiroyuki Ino , Yasuyuki Chaki , Toshiyuki Nakagawa
IPC分类号： G11B20/14 , H03M5/14 , H03M7/40 , H03M5/18
CPC分类号： G11B20/1426 , H03M5/145
摘要： A modulating method and apparatus and a demodulating method and apparatus wherein high density recording can be achieved and a dc component can be controlled with a variable length channel code are disclosed. Recording data are divided into a predetermined plurality of blocks, and those of the recording data at a portion other than a boundary portion of each of the blocks are coded referring to a table of a first ROM so that data of m bits may be converted into a code of n bits. The remaining data at the boundary portion of each block are converted into a code referring to another table of second ROM so that data of m bits may be converted into a code of n bits. Further, a code of n bits for minimizing a dc component is produced referring to a third table of a further ROM and is added to the code generated by the first and second ROMs.
摘要翻译：公开了可以实现高密度记录并且可以用可变长度信道码来控制直流分量的调制方法和装置以及解调方法和装置。记录数据被划分为预定的多个块，并且在每个块的边界部分之外的部分处的记录数据的那些被编码，参考第一ROM的表，使得m位的数据可以被转换成 n位的代码。每个块的边界部分的剩余数据被转换成参考第二ROM的另一个表的代码，使得m位的数据可以被转换成n位的代码。此外，参考另一ROM的第三表产生用于最小化直流分量的n位的代码，并将其添加到由第一和第二ROM产生的代码中。

10. 发明授权

US07526032B2 Sync signal insertion that breaks a maximum bit-run and has a particular detection distance between two or more sync patterns 失效
标题翻译：同步信号插入打破了最大位运行，并具有两个或多个同步模式之间的特定检测距离
公开(公告)号：US07526032B2
公开(公告)日：2009-04-28
申请号：US11811023
申请日：2007-06-08
申请人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
发明人： Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara
IPC分类号： H04B14/04
CPC分类号： G11B20/1426 , G11B20/1403 , G11B2020/1287 , G11B2020/1453 , G11B2020/1457 , H03M5/145 , H04L7/0083 , H04L7/041 , H04L7/044
摘要： Data having a basic data length of m bits is modulated to a variable-length code having a basic code length of n bits. A sync signal is added to the data after a minimum bit-run in the data. The sync signal exhibits two or more patterns, each pattern breaking a maximum bit-run and having six channel bits for identifying each sync signal. The two or more patterns are distinguished from one another, with a detection distance of at least two therebetween.
摘要翻译：具有m比特的基本数据长度的数据被调制为具有n比特的基本码长度的可变长度码。在数据中的最小位运行之后，将同步信号添加到数据。同步信号表现出两种或多种模式，每种模式破坏最大位运行并具有六个通道位用于识别每个同步信号。两个或更多个图案彼此区分，其间的检测距离至少为两个。

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