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    • 3. 发明申请
    • CONTROLLED DEPTH ETCHED VIAS
    • 控制深度蚀刻VIAS
    • US20070062730A1
    • 2007-03-22
    • US11306730
    • 2006-01-09
    • Thomas Murry
    • Thomas Murry
    • H05K1/11
    • H05K1/115H05K3/062H05K3/064H05K3/427H05K3/429H05K2201/09645H05K2203/1184H05K2203/1394H05K2203/1476
    • A printed circuit board (20) includes a sub-assembly having dielectric (22) and conductive layers (24). A hole (26) extends into the sub-assembly. Metal plating (32) is applied on a barrel (27) of the hole (26). A conductive layer (32) and an etch resist (34) are applied to a first photoresist (30) on the hole barrel (27). The first photoresist (30) is removed and a second photoresist (36) is applied leaving areas to be controlled depth etched exposed. The exposed areas (38) are chemically etched. The second layer of photoresist (36) is removed and a second chemical etch operation is performed to define previously plated features (40) on the sub-assembly (20). The etch resist (34) is then removed.
    • 印刷电路板(20)包括具有电介质(22)和导电层(24)的子组件。 孔(26)延伸到子组件中。 金属电镀(32)施加在孔(26)的筒体(27)上。 将导电层(32)和抗蚀剂(34)施加到孔镜筒(27)上的第一光致抗蚀剂(30)上。 去除第一光致抗蚀剂(30)并施加第二光致抗蚀剂(36),留下要被深度蚀刻曝光的区域。 曝光区域(38)被化学蚀刻。 去除第二层光致抗蚀剂(36),并执行第二化学蚀刻操作以在子组件(20)上限定先前镀覆的特征(40)。 然后除去抗蚀剂(34)。