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1. 发明授权

US5656961A High frequency clock signal distribution with high voltage output 失效
标题翻译：高频时钟信号分配具有高电压输出
公开(公告)号：US5656961A
公开(公告)日：1997-08-12
申请号：US135086
申请日：1993-10-12
申请人： Thanh Thien Tran , Clarence Y. Mar , Javier F. Izquierdo
发明人： Thanh Thien Tran , Clarence Y. Mar , Javier F. Izquierdo
IPC分类号： G06F1/10 , H03K19/018 , H03K12/00 , G06F1/04
CPC分类号： G06F1/10 , H03K19/01806
摘要： A clock signal is distributed over a circuit board and across a connector as a sine wave. A circuit located near the clocked circuitry converts the sine wave into a same frequency square wave for use by the clocked circuitry. The output stage of the converter circuitry provides a high output level to drive CMOS circuitry. The output transistor is pulled up to 5 volts, but the preceding transistors are pulled up to 6.3 volts so that the base to emitter drops are compensated.
摘要翻译：时钟信号分布在电路板上，并以连接器的形式分布在正弦波上。位于时钟电路附近的电路将正弦波转换成相同的频率方波，供时钟电路使用。转换器电路的输出级提供高输出电平来驱动CMOS电路。输出晶体管被上拉至5伏特，但是先前的晶体管被上拉至6.3伏，从而补偿基极到发射极的下降。

2. 发明授权

US5281861A Sine wave clock distribution with high voltage output 失效
标题翻译：正弦波时钟分配具有高电压输出
公开(公告)号：US5281861A
公开(公告)日：1994-01-25
申请号：US855453
申请日：1992-03-19
申请人： Thanh T. Tran , Clarence Y. Mar , Javier F. Izquierdo
发明人： Thanh T. Tran , Clarence Y. Mar , Javier F. Izquierdo
IPC分类号： G06F1/10 , H03K19/018 , H03K5/00 , H03B19/00 , H03K5/13 , H03K7/00
CPC分类号： G06F1/10 , H03K19/01806
摘要： A clock signal is distributed over a circuit board and across a connector as a sine wave. A circuit located near the clocked circuitry converts the sine wave into a same frequency square wave for use by the clocked circuitry. The output stage of the converter circuitry provides a high output level to drive CMOS circuitry. The output transistor is pulled up to 5 volts, but the preceding transistors are pulled up to 6.3 volts so that the base to emitter drops are compensated.
摘要翻译：时钟信号分布在电路板上，并以连接器的形式分布在正弦波上。位于时钟电路附近的电路将正弦波转换成相同的频率方波，供时钟电路使用。转换器电路的输出级提供高输出电平来驱动CMOS电路。输出晶体管被上拉至5伏特，但是先前的晶体管被上拉至6.3伏，从而补偿基极到发射极的下降。

3. 发明授权

US4277675A Non-sequential counter 失效
标题翻译：非顺序计数器
公开(公告)号：US4277675A
公开(公告)日：1981-07-07
申请号：US23369
申请日：1979-03-23
申请人： Clarence Y. Mar , Michael J. Caruso
发明人： Clarence Y. Mar , Michael J. Caruso
IPC分类号： H03K23/22
CPC分类号： H03K21/18
摘要： Disclosed is a non-sequential counter. The non-sequential counter comprises, in a preferred embodiment, six inverters coupled together as a three stage shift counter, the input of which is generated according to a feedback term provided by the outputs of each one of the inverter stages. Counters having more than three stages are also disclosed. The feedback term is provided by disclosed decoder circuitry. The non-sequential counter counts through all possible states; thus, a counter having N stages will count non-sequentially through 2.sup.N possible binary states.
摘要翻译：公开了一种非顺序计数器。在优选实施例中，非顺序计数器包括作为三级移位计数器耦合在一起的六个反相器，其输入根据由每个逆变器级的输出提供的反馈项产生。还公开了具有三级以上的计数器。反馈项由公开的解码器电路提供。非顺序计数器通过所有可能的状态计数; 因此，具有N个级的计数器将非依次计数2N个可能的二进制状态。

4. 发明授权

US06792553B2 CPU power sequence for large multiprocessor systems 有权
标题翻译：大型多处理器系统的CPU电源顺序
公开(公告)号：US06792553B2
公开(公告)日：2004-09-14
申请号：US09751506
申请日：2000-12-29
申请人： Clarence Y. Mar , Sompong P. Olarig , John E. Jenne
发明人： Clarence Y. Mar , Sompong P. Olarig , John E. Jenne
IPC分类号： G06F126
CPC分类号： G06F1/305 , G06F1/26
摘要： A computer system includes a power supply coupled to a control logic, the power supply including a power_good output signal and Power output lines. The power_good signal notifies the control logic when the Power output lines have stabilized. The computer system also includes a plurality of voltage regulator modules (“VRM”) coupled to the control logic, wherein each VRM receives a power good signal from the control logic. A plurality of processors is also present in the computer system, each of the processors coupled to a VRM. Each of the VRMs transmits voltage to a processor to power-on the processor. Each VRM also transmits to its processor and to the control logic a voltage regulator module power good (“VRMP_G”) signal. The control logic includes means to control the sequential power-on of the processors so as to reduce the current sourcing requirements of the power supply and eliminate power supply surges.
摘要翻译：计算机系统包括耦合到控制逻辑的电源，电源包括power_good输出信号和电力输出线。当电源输出线路稳定时，power_good信号通知控制逻辑。计算机系统还包括耦合到控制逻辑的多个电压调节器模块（“VRM”），其中每个VRM从控制逻辑接收功率良好信号。计算机系统中还存在多个处理器，每个处理器耦合到VRM。每个VRM将电压传输到处理器以对处理器通电。每个VRM还向其处理器和控制逻辑发送电压调节器模块电源良好（“VRMP_G”）信号。控制逻辑包括用于控制处理器的顺序上电的装置，以便减少电源的电流采购要求并消除电源浪涌。

5. 发明授权

US6101322A Removal and insertion of expansion cards in a computer system 失效
标题翻译：在计算机系统中移除和插入扩展卡
公开(公告)号：US6101322A
公开(公告)日：2000-08-08
申请号：US658538
申请日：1996-06-05
申请人： Alan L. Goodrum , Paul R. Culley , Raymond Y. L. Chow , Barry S. Basile , Richard O. Waldorf , Pamela M. Cook , Clarence Y. Mar
发明人： Alan L. Goodrum , Paul R. Culley , Raymond Y. L. Chow , Barry S. Basile , Richard O. Waldorf , Pamela M. Cook , Clarence Y. Mar
IPC分类号： G06F1/26 , G06F1/18 , G06F1/24 , G06F13/40 , G06F13/00 , G06F1/16
CPC分类号： G06F13/4081
摘要： A method for powering up a removable circuit card when it is inserted into a card slot of a computer system includes providing power and a clock signal to the circuit card. A communication link is electrically coupled to the circuit card after both the power and the clock signal are provided to the circuit card.
摘要翻译：将可移除电路卡插入计算机系统的卡插槽时为其供电的方法包括向电路卡提供电力和时钟信号。在将电源和时钟信号提供给电路卡之后，通信链路电耦合到电路卡。

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