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1. 发明申请

US20110108923A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110108923A1
公开(公告)日：2011-05-12
申请号：US12938662
申请日：2010-11-03
申请人： Yoshitaka KUBOTA , Hiroshi TSUDA , Kenichi HIDAKA , Takuji ONUMA , Hiromichi TAKAOKA
发明人： Yoshitaka KUBOTA , Hiroshi TSUDA , Kenichi HIDAKA , Takuji ONUMA , Hiromichi TAKAOKA
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/0629 , H01L23/5252 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device has a conventional NMOS transistor and an NMOS transistor functioning as an anti-fuse element and having an n type channel region. The conventional NMOS transistor is equipped with an n type extension region and a p type pocket region, while the anti-fuse element is not equipped with an extension region and a pocket region. This makes it possible to improve the performance of the transistor and at the same time improve the characteristics of the anti-fuse element after breakdown of its gate dielectric film.
摘要翻译：半导体器件具有常规的NMOS晶体管和用作反熔丝元件并具有n型沟道区的NMOS晶体管。传统的NMOS晶体管配备有n型延伸区域和p型袋区域，而反熔丝元件没有配备延伸区域和口袋区域。这使得可以提高晶体管的性能，同时提高其栅极电介质膜击穿之后的抗熔丝元件的特性。

2. 发明申请

US20120026810A1 SEMICONDUCTOR MEMORY DEVICE AND ANTIFUSE PROGRAMMING METHOD 有权
标题翻译：半导体存储器件和抗病毒编程方法
公开(公告)号：US20120026810A1
公开(公告)日：2012-02-02
申请号：US13193186
申请日：2011-07-28
申请人： Takuji ONUMA , Kenichi HIDAKA , Hiromichi TAKAOKA , Yoshitaka KUBOTA , Hiroshi TSUDA
发明人： Takuji ONUMA , Kenichi HIDAKA , Hiromichi TAKAOKA , Yoshitaka KUBOTA , Hiroshi TSUDA
IPC分类号： G11C7/00
CPC分类号： G11C17/18
摘要： An antifuse comprised of an NMOS transistor or an NMOS capacitor includes a first terminal coupled to a gate electrode, a second terminal coupled to a diffusion layer, and a gate insulating film interposed between the gate electrode and the diffusion layer. A programming circuit includes a first programming circuit which has first current drive capability and which performs first programming operation and a second programming circuit which has second current drive capability larger than the first current drive capability and which performs second programming operation to follow the first programming operation. In the first programming operation, the first programming circuit breaks down the gate insulating film by applying a first programming voltage between the first terminal and the second terminal. In the second programming operation, the second programming circuit applies a second programming voltage lower than the first programming voltage between the first terminal and the second terminal.
摘要翻译：由NMOS晶体管或NMOS电容器构成的反熔丝包括耦合到栅电极的第一端子，耦合到扩散层的第二端子和介于栅极电极和扩散层之间的栅极绝缘膜。编程电路包括具有第一电流驱动能力并执行第一编程操作的第一编程电路和具有大于第一电流驱动能力的第二电流驱动能力的第二编程电路，并且执行第二编程操作以跟随第一编程操作。在第一编程操作中，第一编程电路通过在第一端子和第二端子之间施加第一编程电压来分解栅极绝缘膜。在第二编程操作中，第二编程电路在第一端子和第二端子之间施加低于第一编程电压的第二编程电压。

3. 发明申请

US20120080736A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20120080736A1
公开(公告)日：2012-04-05
申请号：US13250516
申请日：2011-09-30
申请人： Takuji ONUMA , Kenichi HIDAKA , Hiromichi TAKAOKA , Yoshitaka KUBOTA , Hiroshi TSUDA , Kiyokazu ISHIGE
发明人： Takuji ONUMA , Kenichi HIDAKA , Hiromichi TAKAOKA , Yoshitaka KUBOTA , Hiroshi TSUDA , Kiyokazu ISHIGE
IPC分类号： H01L29/78
CPC分类号： H01L27/11206 , G11C17/16 , H01L23/5252 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： An antifuse whose internal written information cannot be analyzed even by utilizing methods to determine whether there is a charge-up in the electrodes. The antifuse includes a gate insulation film, a gate electrode, and a first diffusion layer. A second diffusion layer is isolated from the first diffusion layer by way of a device isolator film, and is the same conduction type as the first diffusion layer. The gate wiring is formed as one integrated piece with the gate electrode, and extends over the device isolator film. A common contact couples the gate wiring to the second diffusion layer. The gate electrode is comprised of semiconductor material such as polysilicon that is doped with impurities of the same conduction type as the first diffusion layer. The second diffusion layer is coupled only to the common contact.
摘要翻译：即使利用确定电极中是否有电荷的方法，内部书面信息也无法分析的反熔丝。反熔丝包括栅极绝缘膜，栅电极和第一扩散层。第二扩散层通过器件隔离膜从第一扩散层隔离，并且是与第一扩散层相同的导电类型。栅极布线形成为与栅极电极一体化的部件，并且在器件隔离膜上延伸。常见的接触将栅极布线耦合到第二扩散层。栅电极由掺杂有与第一扩散层相同导电类型的杂质的多晶硅等半导体材料构成。第二扩散层仅耦合到公共接触。

4. 发明申请

US20130033921A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130033921A1
公开(公告)日：2013-02-07
申请号：US13566575
申请日：2012-08-03
申请人： Hiroshi TSUDA , Yoshitaka KUBOTA , Kenichi HIDAKA , Hiromichi TAKAOKA
发明人： Hiroshi TSUDA , Yoshitaka KUBOTA , Kenichi HIDAKA , Hiromichi TAKAOKA
IPC分类号： G11C11/00
CPC分类号： G11C7/24 , G06F21/75 , G06F21/79 , G11C13/0004 , G11C13/003 , G11C13/0059 , G11C17/16 , G11C2213/74 , G11C2213/79 , H01L23/5252 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device using resistive random access memory (ReRAM) elements and having improved tamper resistance is provided. The semiconductor device is provided with a unit cell which stores one bit of cell data and a control circuit. The unit cell includes n ReRAM elements (n being an integer of 2 or larger). At least one of the ReRAM elements is an effective element where the cell data is recorded. In reading the cell data, the control circuit at least selects the effective element and reads data recorded thereon as the cell data.
摘要翻译：提供了一种使用电阻随机存取存储器（ReRAM）元件并具有改进的防篡改性的半导体器件。半导体器件设置有存储一位单元数据的单元单元和控制电路。单位单元包括n个ReRAM元素（n是2或更大的整数）。 ReRAM元素中的至少一个是记录单元数据的有效元素。在读取单元数据时，控制电路至少选择有效元件并将其上记录的数据读取为单元数据。

5. 发明申请

US20130058150A1 OTP MEMORY 有权
公开(公告)号：US20130058150A1
公开(公告)日：2013-03-07
申请号：US13584899
申请日：2012-08-14
申请人： Kenichi HIDAKA , Yoshitaka KUBOTA
发明人： Kenichi HIDAKA , Yoshitaka KUBOTA
IPC分类号： G11C17/16 , G11C17/04
CPC分类号： H01L27/11206 , G11C17/16 , G11C17/18 , H01L28/40
摘要： The present invention provides an OTP memory having higher confidentiality. A memory cell has a memory transistor forming a current path between first and second nodes, a selection transistor forming a current path between third and fourth nodes, the third node being coupled to the gate of the memory transistor via a line, and a capacitor coupled to the first node. By applying high voltage which does not break but deteriorates a gate oxide film and increases gate leak current to a memory transistor, data is written. Data can be read by the presence/absence of leak of charges accumulated in the capacitor. Since the position of deterioration in the gate oxide film cannot be discriminated by a physical analysis, confidentiality is high.

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