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1. 发明授权

US06600198B2 Electrostatic discharge protection circuit for a semiconductor device 失效
标题翻译：一种半导体器件的静电放电保护电路
公开(公告)号：US06600198B2
公开(公告)日：2003-07-29
申请号：US09946492
申请日：2001-09-06
申请人： Takahiro Ohnakado , Satoshi Yamakawa
发明人： Takahiro Ohnakado , Satoshi Yamakawa
IPC分类号： H01L2362
CPC分类号： H01L21/82385 , H01L21/823871 , H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having high ESD resistance includes an internal circuit, an I/O pad, a division circuit connected to a lead-in line connecting the internal circuit and the I/O pad for outputting an electric signal from first and second terminals corresponding to an electric signal applied to the lead-in line and a clamp circuit including an MOS transistor for cutting off conduction when a difference in voltage between electric signals sent between the terminals is smaller in absolute value than a threshold voltage of the MOS transistor, and conducts when the absolute value is at least equal to the threshold voltage.
摘要翻译：具有高ESD电阻的半导体器件包括内部电路，I / O焊盘，连接到连接内部电路和I / O焊盘的引入线的分割电路，用于从对应于第一和第二端子的第一和第二端子输出电信号施加到引入线的电信号和包括用于在端子之间发送的电信号之间的电压差在MOS晶体管的阈值电压下绝对值小的用于截断导通的MOS晶体管的钳位电路，并且导通当绝对值至少等于阈值电压时。

2. 发明授权

US06847511B2 Circuit protecting against electrostatic discharge 失效
标题翻译：电路防静电放电
公开(公告)号：US06847511B2
公开(公告)日：2005-01-25
申请号：US10066608
申请日：2002-02-06
申请人： Takahiro Ohnakado , Tatsuo Oomori
发明人： Takahiro Ohnakado , Tatsuo Oomori
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L27/02 , H01L27/06 , H01L27/092 , H02H9/00
CPC分类号： H01L27/0266 , H01L27/0251
摘要： A quarter wavelength transmission line is provided between a signal transmission line for transmitting a high frequency signal and a ground node. The quarter wavelength transmission line has a length equal to a quarter of an effective wavelength of an operation frequency of a semiconductor device. A surge absorbing element is connected between the quarter wavelength transmission line and an internal circuit. The signal transmission line is coupled to the internal circuit through a capacitor. A clamp circuit is provided between a power supply line and a ground line. The clamp circuit clamps the voltage difference between the power supply line and the ground line to a prescribed voltage level or less. A high frequency semiconductor device is thus implemented which is capable of preventing breakdown of an internal circuit element due to an electrostatic discharge phenomenon (ESD) without degrading high frequency characteristics.
摘要翻译：在用于发送高频信号的信号传输线和接地节点之间提供四分之一波长的传输线。四分之一波长传输线具有等于半导体器件的工作频率的有效波长的四分之一的长度。浪涌吸收元件连接在四分之一波长传输线和内部电路之间。信号传输线通过电容耦合到内部电路。在电源线和接地线之间设置钳位电路。钳位电路将电源线和接地线之间的电压差钳位到规定的电压电平以下。因此，可以实现能够防止由于静电放电现象（ESD）而导致的内部电路元件的破坏而不降低高频特性的高频半导体器件。

3. 发明授权

US06844596B2 Si-MOS high-frequency semiconductor device 失效
标题翻译： Si-MOS高频半导体器件
公开(公告)号：US06844596B2
公开(公告)日：2005-01-18
申请号：US09911581
申请日：2001-07-25
申请人： Takahiro Ohnakado
发明人： Takahiro Ohnakado
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L23/62 , H01L27/02 , H01L27/06 , H01L27/092 , H01L27/148 , H01L29/78 , H01L29/861
CPC分类号： H01L27/0255 , H01L27/0629 , H01L2924/0002 , H01L2924/00
摘要： A sophisticated and highly reliable high-frequency Si-MOS semiconductor device having high electrostatic discharge (ESD) resistance. Lateral polysilicon diodes are connected between high-frequency I/O signal lines and the external supply voltage, VDD, and between the ground, GND, and the high-frequency I/O signal lines, respectively. The forward direction of the diodes is the direction from the high-frequency I/O signal line to the supply voltage, VDD, and the direction from the ground, GND, to the high-frequency I/O signal line, respectively.
摘要翻译：具有高静电放电（ESD）电阻的复杂且高度可靠的高频Si-MOS半导体器件。侧向多晶硅二极管分别连接在高频I / O信号线和外部电源VDD之间，以及地，GND和高频I / O信号线之间。二极管的正向是从高频I / O信号线到电源电压VDD以及从地，GND到高频I / O信号线的方向。

4. 发明授权

US06734509B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06734509B2
公开(公告)日：2004-05-11
申请号：US10274451
申请日：2002-10-21
申请人： Takahiro Ohnakado , Akihiko Furukawa
发明人： Takahiro Ohnakado , Akihiko Furukawa
IPC分类号： H01L2972
CPC分类号： H01L21/823807 , H01L21/823892 , H01L27/0921 , H03K17/693
摘要： A semiconductor integrated circuit device includes a silicon substrate having a first region and a second region identical in conductivity type to the first region and having a lower dopant concentration than the first region, a second MOS transistor on a main surface of the second region as a radio frequency switch circuit switching on and off input and output of a radio frequency signal, and a first MOS transistor on a main surface of the first region in a radio frequency circuit other than the radio frequency switch circuit. A high performance, highly reliable semiconductor integrated circuit with an RE switch circuit provided on a silicon substrate as a system on a chip.
摘要翻译：半导体集成电路器件包括具有第一区域和第二区域的硅衬底，第二区域和第二区域的导电类型与第一区域相同，并且具有比第一区域低的掺杂剂浓度;第二区域的主表面上的第二MOS晶体管为无线电频率开关电路接通和断开射频信号的输入和输出，以及在射频切换电路以外的射频电路中的第一区域的主表面上的第一MOS晶体管。一种高性能，高可靠性的半导体集成电路，其具有在作为芯片上的系统的硅衬底上提供的RE开关电路。

5. 发明申请

US20050206371A1 Rotation state detecting device and rotation state detecting method 有权
标题翻译：旋转状态检测装置和旋转状态检测方法
公开(公告)号：US20050206371A1
公开(公告)日：2005-09-22
申请号：US11076874
申请日：2005-03-11
申请人： Manabu Tsukamoto , Takaaki Murakami , Yuji Ariyoshi , Takahiro Ohnakado , Yasuhiro Kosasayama
发明人： Manabu Tsukamoto , Takaaki Murakami , Yuji Ariyoshi , Takahiro Ohnakado , Yasuhiro Kosasayama
IPC分类号： G01P3/488 , G01B7/14 , G01B7/30 , G01D5/12 , G01D5/14 , G01D5/16 , G01D5/244 , G01D5/245 , G01P13/04 , G01R33/06
CPC分类号： G01D5/145 , G01D5/2451
摘要： A rotation state detecting device capable of detecting the direction of rotation of a rotating body includes first and second bridge circuits made up of magneto-resistance effect elements, a first comparator for detecting the increasing/decreasing direction of the center point voltage of the first bridge circuit, a second comparator for detecting the increasing/decreasing direction of the center point voltage of the second bridge circuit, a third comparator for detecting the difference between the center point voltage of the first bridge circuit and the center point voltage of the second bridge circuit, and logic value information deriving means for outputting “1” when the logic values of the outputs of the first comparator and the second comparator are both “1”, outputting “0” when they are both “0”, and continuing to output the previous value at other times, the direction of rotation of the rotating body being determined on the basis of a combination of the outputs of the first, second and third comparators and the logic value information deriving means.
摘要翻译：能够检测旋转体的旋转方向的旋转状态检测装置包括由磁阻效应元件构成的第一和第二桥接电路，用于检测第一桥的中心点电压的增减方向的第一比较器电路，用于检测第二桥接电路的中心点电压的增加/减少方向的第二比较器，用于检测第一桥接电路的中心点电压与第二桥接电路的中心点电压之间的差的第三比较器以及当第一比较器和第二比较器的输出的逻辑值都为“1”时输出“1”的逻辑值信息导出装置，当它们均为“0”时输出“0”，并且继续输出在其他时刻的先前值，旋转体的旋转方向基于第一，第二的输出的组合来确定 nd和第三比较器以及逻辑值信息导出装置。

6. 发明授权

US5901084A Nonvolatile semiconductor memory device having floating gate electrode 失效
标题翻译：具有浮栅电极的非易失性半导体存储器件
公开(公告)号：US5901084A
公开(公告)日：1999-05-04
申请号：US933764
申请日：1997-09-23
申请人： Takahiro Ohnakado
发明人： Takahiro Ohnakado
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , G11C16/04
CPC分类号： H01L29/7883 , H01L29/42324
摘要： A nonvolatile semiconductor memory device is obtained of which tunnel oxide film can be made thinner and which can allow low voltage and power consumption. P type polycrystal silicon is used as a floating gate electrode. Thickness of a tunnel oxide film (first insulating film) is set to less than 10 nm. By using P type polysilicon as a material of the floating gate electrode, a barrier height of a well-type potential is increased from 3.1 eV to 4.4 eV, and thus the leak current is effectively prevented. Thus, the film thickness of the tunnel oxide film can be made less than 10 nm, and operating voltage can also be lowered. Therefore, reduction in power consumption and improvement in performance of the nonvolatile semiconductor memory device can be achieved.
摘要翻译：获得了可以使隧道氧化膜更薄并且可以允许低电压和功率消耗的非易失性半导体存储器件。 P型多晶硅用作浮栅电极。隧道氧化膜（第一绝缘膜）的厚度设定为小于10nm。通过使用P型多晶硅作为浮栅电极的材料，阱型势垒的势垒高度从3.1eV提高到4.4eV，从而有效地防止漏电流。因此，可以使隧道氧化膜的膜厚小于10nm，工作电压也可以降低。因此，可以实现功率消耗的降低和非易失性半导体存储器件的性能的提高。

7. 发明授权

US07205761B2 Rotation state detecting device and rotation state detecting method 有权
标题翻译：旋转状态检测装置和旋转状态检测方法
公开(公告)号：US07205761B2
公开(公告)日：2007-04-17
申请号：US11076874
申请日：2005-03-11
申请人： Manabu Tsukamoto , Takaaki Murakami , Yuji Ariyoshi , Takahiro Ohnakado , Yasuhiro Kosasayama
发明人： Manabu Tsukamoto , Takaaki Murakami , Yuji Ariyoshi , Takahiro Ohnakado , Yasuhiro Kosasayama
IPC分类号： G01P3/44 , G01B7/30 , G08B21/00
CPC分类号： G01D5/145 , G01D5/2451
摘要： A rotation state detecting device capable of detecting the direction of rotation of a rotating body includes first and second bridge circuits made up of magneto-resistance effect elements, a first comparator for detecting the increasing/decreasing direction of the center point voltage of the first bridge circuit, a second comparator for detecting the increasing/decreasing direction of the center point voltage of the second bridge circuit, a third comparator for detecting the difference between the center point voltage of the first bridge circuit and the center point voltage of the second bridge circuit, and logic value information deriving means for outputting “1” when the logic values of the outputs of the first comparator and the second comparator are both “1”, outputting “0” when they are both “0”, and continuing to output the previous value at other times, the direction of rotation of the rotating body being determined on the basis of a combination of the outputs of the first, second and third comparators and the logic value information deriving means.
摘要翻译：能够检测旋转体的旋转方向的旋转状态检测装置包括由磁阻效应元件构成的第一和第二桥接电路，用于检测第一桥的中心点电压的增减方向的第一比较器电路，用于检测第二桥接电路的中心点电压的增加/减少方向的第二比较器，用于检测第一桥接电路的中心点电压与第二桥接电路的中心点电压之间的差的第三比较器以及当第一比较器和第二比较器的输出的逻辑值都为“1”时输出“1”的逻辑值信息导出装置，当它们均为“0”时输出“0”，并且继续输出在其他时刻的先前值，旋转体的旋转方向基于第一，第二的输出的组合来确定 nd和第三比较器以及逻辑值信息导出装置。

8. 发明授权

US06635920B2 Non-volatile semiconductor memory device and manufacturing method thereof 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US06635920B2
公开(公告)日：2003-10-21
申请号：US09769465
申请日：2001-01-26
申请人： Takahiro Ohnakado , Atsushi Fukumoto , Satoshi Shimizu
发明人： Takahiro Ohnakado , Atsushi Fukumoto , Satoshi Shimizu
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/66825
摘要： Memory cell gates are formed on the main surface of a semiconductor substrate via a gate isolation film. Source regions and drain regions are formed on both sides of the memory cell gates. The source regions have p− impurity regions and n+ impurity regions while the drain regions have p− impurity regions and n+ impurity regions. And the concentration of the p− impurity regions is made higher than the concentration of the p− regions while the concentration of the n+ impurity regions is made higher than the concentration of the n+ impurity regions.
摘要翻译：存储单元栅极经由栅极隔离膜形成在半导体衬底的主表面上。源极区和漏极区形成在存储单元栅极的两侧。源区具有p < - >杂质区和n + +杂质区，而漏区具有p +杂质区和n +杂质区。并且使p + - 杂质区域的浓度高于p +区域的浓度，同时使n + +杂质区域的浓度高于n + +杂质区域的浓度。

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