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1. 发明公开

US20240339544A1 LIGHTLY-DOPED CHANNEL EXTENSIONS 审中-公开
公开(公告)号：US20240339544A1
公开(公告)日：2024-10-10
申请号：US18744952
申请日：2024-06-17
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Wei-Jen Lai , Wei-Yuan Lu , Chih-Hao Yu , Chia-Pin Lin
IPC分类号： H01L29/786 , H01L29/06 , H01L29/08 , H01L29/165 , H01L29/423 , H01L29/66 , H01L29/78
CPC分类号： H01L29/78696 , H01L29/0653 , H01L29/42392 , H01L29/66545 , H01L29/66553 , H01L29/66742 , H01L29/66787 , H01L29/7848 , H01L29/78621 , H01L29/0847 , H01L29/165 , H01L29/78684
摘要： A semiconductor structure and a method of forming the same are provided. A semiconductor structure according to the present disclosure includes a first channel member and a second channel member disposed over the first channel member, a first channel extension feature coupled to the first channel member, a second channel extension feature coupled to the second channel member, and an inner spacer feature disposed between the first channel extension feature and the second channel extension feature.

2. 发明授权

US12027626B2 Semiconductor device active region profile and method of forming the same 有权
公开(公告)号：US12027626B2
公开(公告)日：2024-07-02
申请号：US18066188
申请日：2022-12-14
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Feng-Ching Chu , Wei-Yang Lee , Chia-Pin Lin
IPC分类号： H01L29/78 , H01L21/3065 , H01L21/3213 , H01L21/762 , H01L29/06 , H01L29/10 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L29/7856 , H01L21/3065 , H01L21/32134 , H01L21/76224 , H01L29/0673 , H01L29/1037 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/66818 , H01L29/775 , H01L29/78618 , H01L29/78696
摘要： Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method of manufacture comprises receiving a substrate including a semiconductor material stack formed thereon, wherein the semiconductor material stack includes a first semiconductor layer of a first semiconductor material and second semiconductor layer of a second semiconductor material that is different than the first semiconductor material. Patterning the semiconductor material stack to form a trench. The patterning includes performing a first etch process with a first etchant for a first duration and then performing a second etch process with a second etchant for a second duration, where the second etchant is different from the first etchant and the second duration is greater than the first duration. The first etch process and the second etch process are repeated a number of times. Then epitaxially growing a third semiconductor layer of the first semiconductor material on a sidewall of the trench.

3. 发明公开

US20240186373A1 EPITAXIAL STRUCTURES EXPOSED IN AIRGAPS FOR SEMICONDUCTOR DEVICES 审中-公开
公开(公告)号：US20240186373A1
公开(公告)日：2024-06-06
申请号：US18434914
申请日：2024-02-07
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Po-Yu Lin , Wei-Yang Lee , Chia-Pin Lin , Tzu-Hua Chiu , Kuan-Hao Cheng , Wei-Han Fan , Li-Li Su , Wei-Min Liu
IPC分类号： H01L29/06 , H01L21/02 , H01L21/306 , H01L29/423 , H01L29/66 , H01L29/786
CPC分类号： H01L29/0653 , H01L29/66553 , H01L29/66742 , H01L29/78696 , H01L21/02532 , H01L21/02639 , H01L21/30604 , H01L29/0665 , H01L29/42392
摘要： A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.

4. 发明授权

US12002845B2 Method of manufacturing a semiconductor device and a semiconductor device 有权
公开(公告)号：US12002845B2
公开(公告)日：2024-06-04
申请号：US17575145
申请日：2022-01-13
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Ting-Yeh Chen , Wei-Yang Lee , Chia-Pin Lin , Yuan-Ching Peng
IPC分类号： H01L29/76 , H01L23/64 , H01L27/08 , H01L29/00 , H01L29/06 , H01L49/02
CPC分类号： H01L28/20 , H01L23/647 , H01L27/0802 , H01L29/0649
摘要： In a method of manufacturing a semiconductor device, a fin structure, which includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, is formed. An isolation insulating layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed. A third dielectric layer is formed on the recessed second dielectric layer. The third dielectric layer is partially removed to form a trench. A fourth dielectric layer is formed by filling the trench with a dielectric material, thereby forming a wall fin structure.

5. 发明申请

US20220285510A1 Semiconductor Device with Backside Contact and Methods of Forming Such 有权
公开(公告)号：US20220285510A1
公开(公告)日：2022-09-08
申请号：US17375264
申请日：2021-07-14
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ting-Yeh Chen , Yen-Ting Chen , Wei-Yang Lee , Chia-Pin Lin
IPC分类号： H01L29/423 , H01L29/786 , H01L29/06 , H01L21/8234 , H01L29/66
摘要： In an exemplary aspect, the present disclosure is directed to a device. The device includes a fin-shaped structure extending lengthwise along a first direction. The fin-shaped structure includes a stack of semiconductor layers arranged one over another along a second direction perpendicular to the first direction. The device also includes a first source/drain feature of a first dopant type on the fin-shaped structure and spaced away from the stack of semiconductor layers. The device further includes a second source/drain feature of a second dopant type on the fin-shaped structure over the first source/drain feature along the second direction and connected to the stack of semiconductor layers. The second dopant type is different from the first dopant type. Furthermore, the device additionally includes an isolation feature interposing between the first source/drain feature and the second source/drain features.

6. 发明申请

US20220262683A1 SEMICONDUCTOR STRUCTURE WITH GATE-ALL-AROUND DEVICES AND STACKED FINFET DEVICES 有权
公开(公告)号：US20220262683A1
公开(公告)日：2022-08-18
申请号：US17739925
申请日：2022-05-09
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Feng-Ching Chu , Wei-Yang Lee , Chia-Pin Lin
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/423 , H01L29/786 , H01L29/66 , H01L21/02
摘要： An integrated circuit (IC) includes a substrate and a first transistor on the substrate. The first transistor includes two first source/drain features, a stack of first semiconductor layers and second semiconductor layers alternately stacked one over another and disposed between the two first source/drain features, a first gate dielectric layer disposed over top and sidewalls of the stack of the first and the second semiconductor layers, a first gate electrode layer disposed over the first gate dielectric layer, and first spacer features disposed laterally between each of the second semiconductor layers and each of the two first source/drain features and electrically isolating each of the second semiconductor layers from each of the two first source/drain features. The first semiconductor layers electrically connect the two first source/drain features.

7. 发明申请

US20220157969A1 Inner Spacer Liner 有权
公开(公告)号：US20220157969A1
公开(公告)日：2022-05-19
申请号：US17097711
申请日：2020-11-13
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jin-Mu Yin , Wei-Yang Lee , Chih-Hao Yu , Yen-Ting Chen , Chia-Pin Lin
IPC分类号： H01L29/66 , H01L29/786 , H01L29/423 , H01L29/78
摘要： The present disclosure provides a semiconductor device and a method of forming the same. A semiconductor device according to the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a semiconductor liner sandwiched between the gate structure and each of the plurality of inner spacer features.

8. 发明授权

US09281356B2 Integrated circuit resistor 有权
标题翻译：集成电路电阻
公开(公告)号：US09281356B2
公开(公告)日：2016-03-08
申请号：US14586013
申请日：2014-12-30
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： King-Yuen Wong , Chia-Pin Lin , Chia-Yu Lu , Yi-Cheng Tsai , Da-Wen Lin , Kuo-Feng Yu
IPC分类号： H01L49/02 , H01L27/06 , H01L29/8605 , H01L21/265 , H01L21/02 , H01L21/8234 , H01L29/66
CPC分类号： H01L28/20 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/26506 , H01L21/26513 , H01L21/823437 , H01L27/0629 , H01L29/66545 , H01L29/8605
摘要： A method of fabricating a semiconductor device is disclosed. The method includes providing a substrate including an isolation region, forming a resistor over the isolation region, and forming a contact over the resistor. The method also includes implanting with a dopant concentration that is step-increased at a depth of the resistor and that remains substantially constant as depth increases.
摘要翻译：公开了制造半导体器件的方法。该方法包括提供包括隔离区域的衬底，在隔离区域上形成电阻器，以及在电阻器上形成接触。该方法还包括以在电阻器的深度处逐步增加的掺杂剂浓度进行注入，并且随着深度增加而保持基本恒定。

9. 发明授权

US08994116B2 Hybrid gate process for fabricating FinFET device 有权
标题翻译：用于制造FinFET器件的混合栅极工艺
公开(公告)号：US08994116B2
公开(公告)日：2015-03-31
申请号：US14083533
申请日：2013-11-19
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tian-Choy Gan , Hsien-Chin Lin , Chia-Pin Lin , Shyue-Shyh Lin , Li-Shiun Chen , Shin Hsien Liao
IPC分类号： H01L27/092 , H01L29/66 , H01L29/78 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/8238 , H01L29/66795 , H01L29/785
摘要： Provided is a method of fabricating a semiconductor device that includes forming first and second fins over first and second regions of a substrate, forming first and second gate structures over the first and second fins, the first and second gate structures including first and second poly gates, forming an inter-level dielectric (ILD) over the substrate, performing a chemical mechanical polishing on the ILD to expose the first and second poly gates, forming a mask to protect the first poly gate of the first gate structure, removing the second poly gate thereby forming a first trench, removing the mask, partially removing the first poly gate thereby forming a second trench, forming a work function metal layer partially filling the first and second trenches, forming a fill metal layer filling a remainder of the first and second trenches, and removing the metal layers outside the first and second trenches.
摘要翻译：提供一种制造半导体器件的方法，该半导体器件包括在衬底的第一和第二区域上形成第一和第二鳍片，在第一和第二鳍片上形成第一和第二栅极结构，第一和第二栅极结构包括第一和第二多晶硅栅极，在所述衬底上形成层间电介质（ILD），在所述ILD上进行化学机械抛光以暴露所述第一和第二多晶硅栅极，形成掩模以保护所述第一栅极结构的所述第一多晶硅栅极，从而形成第一沟槽，去除掩模，部分地移除第一多晶硅栅极，从而形成第二沟槽，形成部分填充第一和第二沟槽的功函数金属层，形成填充第一和第二沟槽的剩余部分的填充金属层沟槽，并且去除第一和第二沟槽外的金属层。

10. 发明授权

US12087837B2 Semiconductor device with backside contact and methods of forming such 有权
公开(公告)号：US12087837B2
公开(公告)日：2024-09-10
申请号：US17375264
申请日：2021-07-14
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ting-Yeh Chen , Yen-Ting Chen , Wei-Yang Lee , Chia-Pin Lin
IPC分类号： H01L29/423 , H01L21/8234 , H01L29/06 , H01L29/66 , H01L29/786
CPC分类号： H01L29/42392 , H01L21/823418 , H01L29/0649 , H01L29/0665 , H01L29/66545 , H01L29/78696
摘要： In an exemplary aspect, the present disclosure is directed to a device. The device includes a fin-shaped structure extending lengthwise along a first direction. The fin-shaped structure includes a stack of semiconductor layers arranged one over another along a second direction perpendicular to the first direction. The device also includes a first source/drain feature of a first dopant type on the fin-shaped structure and spaced away from the stack of semiconductor layers. The device further includes a second source/drain feature of a second dopant type on the fin-shaped structure over the first source/drain feature along the second direction and connected to the stack of semiconductor layers. The second dopant type is different from the first dopant type. Furthermore, the device additionally includes an isolation feature interposing between the first source/drain feature and the second source/drain features.

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