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1. 发明申请

US20180138080A1 HANDLE SUBSTRATE FOR USE IN MANUFACTURE OF SEMICONDUCTOR-ON-INSULATOR STRUCTURE AND METHOD OF MANUFACTURING THEREOF 审中-公开
公开(公告)号：US20180138080A1
公开(公告)日：2018-05-17
申请号：US15850265
申请日：2017-12-21
申请人： SunEdison Semiconductor Limited (UEN201334164H)
发明人： Alex Usenko
IPC分类号： H01L21/762
CPC分类号： H01L21/76254
摘要： A method is provided for preparing a high resistivity silicon handle substrate for use in semiconductor-on-insulator structure. The handle substrate is prepared to comprise thermally stable charge carrier traps in the region of the substrate that will be at or near the buried oxide layer (BOX) of the final semiconductor-on-insulator structure. The handle substrate comprising the stable carrier traps is manufactured by hydrogen ions implantation occurring using at least two different energies, followed by a 2-step thermal treatment. The thermally stable defect structures prepared thereby is stable to anneal at temperatures of at least 1180° C. The defect structure comprises 3-dimensional network of nano-cavities interconnected by dislocations. This wafer can be used as a handle wafer for fabricating silicon-on-insulator (SOI) wafers and further fabricating radio frequency (RF) semiconductor devices.

2. 发明申请

US20160276209A1 HANDLE SUBSTRATE FOR USE IN MANUFACTURE OF SEMICONDUCTOR-ON-INSULATOR STRUCTURE AND METHOD OF MANUFACTURING THEREOF 有权
标题翻译：用于制造半导体绝缘体结构的手柄基板及其制造方法
公开(公告)号：US20160276209A1
公开(公告)日：2016-09-22
申请号：US15070060
申请日：2016-03-15
申请人： SunEdison Semiconductor Limited (UEN201334164H)
发明人： Alex Usenko
IPC分类号： H01L21/762 , H01L29/06
CPC分类号： H01L21/76254
摘要： A method is provided for preparing a high resistivity silicon handle substrate for use in semiconductor-on-insulator structure. The handle substrate is prepared to comprise thermally stable charge carrier traps in the region of the substrate that will be at or near the buried oxide layer (BOX) of the final semiconductor-on-insulator structure. The handle substrate comprising the stable carrier traps is manufactured by hydrogen ions implantation occurring using at least two different energies, followed by a 2-step thermal treatment. The thermally stable defect structures prepared thereby is stable to anneal at temperatures of at least 1180° C. The defect structure comprises 3-dimensional network of nano-cavities interconnected by dislocations. This wafer can be used as a handle wafer for fabricating silicon-on-insulator (SOI) wafers and further fabricating radio frequency (RF) semiconductor devices.
摘要翻译：提供了一种制备用于绝缘体上半导体结构的高电阻率硅处理衬底的方法。处理衬底被准备为在衬底区域内包含热稳定的电荷载流子阱，该区域将处于最终的绝缘体上半导体结构的掩埋氧化物层（BOX）或其附近。通过使用至少两种不同能量进行氢离子注入，然后进行2步热处理，制造包含稳定载流子阱的手柄基板。由此制备的热稳定缺陷结构在至少1180℃的温度下退火是稳定的。缺陷结构包括通过位错相互连接的纳米腔的三维网络。该晶片可以用作制造绝缘体上硅（SOI）晶片并进一步制造射频（RF）半导体器件的处理晶片。

3. 发明授权

US09881832B2 Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof 有权
公开(公告)号：US09881832B2
公开(公告)日：2018-01-30
申请号：US15070060
申请日：2016-03-15
申请人： SunEdison Semiconductor Limited (UEN201334164H)
发明人： Alex Usenko
IPC分类号： H01L21/70 , H01L21/762
CPC分类号： H01L21/76254
摘要： A method is provided for preparing a high resistivity silicon handle substrate for use in semiconductor-on-insulator structure. The handle substrate is prepared to comprise thermally stable charge carrier traps in the region of the substrate that will be at or near the buried oxide layer (BOX) of the final semiconductor-on-insulator structure. The handle substrate comprising the stable carrier traps is manufactured by hydrogen ions implantation occurring using at least two different energies, followed by a 2-step thermal treatment. The thermally stable defect structures prepared thereby is stable to anneal at temperatures of at least 1180° C. The defect structure comprises 3-dimensional network of nano-cavities interconnected by dislocations. This wafer can be used as a handle wafer for fabricating silicon-on-insulator (SOI) wafers and further fabricating radio frequency (RF) semiconductor devices.

4. 发明授权

US10483152B2 High resistivity semiconductor-on-insulator wafer and a method of manufacturing 有权
公开(公告)号：US10483152B2
公开(公告)日：2019-11-19
申请号：US15526640
申请日：2015-11-16
申请人： SunEdison Semiconductor Limited (UEN201334164H)
发明人： Igor Peidous , Lu Fei , Jeffrey L. Libbert , Andrew M. Jones , Alex Usenko , Gang Wang , Shawn George Thomas , Srikanth Kommu
IPC分类号： H01L21/76 , H01L21/762
摘要： A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.

5. 发明申请

US20170316968A1 HIGH RESISTIVITY SEMICONDUCTOR-IN-INSULATOR WAFER AND A METHOD OF MANUFACTURING 审中-公开
公开(公告)号：US20170316968A1
公开(公告)日：2017-11-02
申请号：US15526640
申请日：2015-11-16
申请人： SunEdison Semiconductor Limited (UEN201334164H)
发明人： Igor Peidous , Lu Fei , Jeffrey L. Libbert , Andrew M. Jones , Alex Usenko , Gang Wang , Shawn George Thomas , Srikanth Kommu
IPC分类号： H01L21/762
摘要： A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.

6. 发明授权

US10475694B2 Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof 有权
公开(公告)号：US10475694B2
公开(公告)日：2019-11-12
申请号：US15850265
申请日：2017-12-21
申请人： SunEdison Semiconductor Limited (UEN201334164H)
发明人： Alex Usenko
IPC分类号： H01L21/762
摘要： A method is provided for preparing a high resistivity silicon handle substrate for use in semiconductor-on-insulator structure. The handle substrate is prepared to comprise thermally stable charge carrier traps in the region of the substrate that will be at or near the buried oxide layer (BOX) of the final semiconductor-on-insulator structure. The handle substrate comprising the stable carrier traps is manufactured by hydrogen ions implantation occurring using at least two different energies, followed by a 2-step thermal treatment. The thermally stable defect structures prepared thereby is stable to anneal at temperatures of at least 1180° C. The defect structure comprises 3-dimensional network of nano-cavities interconnected by dislocations. This wafer can be used as a handle wafer for fabricating silicon-on-insulator (SOI) wafers and further fabricating radio frequency (RF) semiconductor devices.

7. 发明授权

US10290533B2 Thermally stable charge trapping layer for use in manufacture of semiconductor-on-insulator structures 有权
公开(公告)号：US10290533B2
公开(公告)日：2019-05-14
申请号：US15557503
申请日：2016-03-11
申请人： SunEdison Semiconductor Limited (UEN201334164H)
发明人： Alex Usenko
IPC分类号： H01L21/762 , H01L27/12 , H01L21/02
摘要： A single crystal semiconductor handle substrate for use in the manufacture of semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) structure is etched to form a porous layer in the front surface region of the wafer. The etched region is oxidized and then filled with a semiconductor material, which may be polycrystalline or amorphous. The surface is polished to render it bondable to a semiconductor donor substrate. Layer transfer is performed over the polished surface thus creating semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) structure having 4 layers: the handle substrate, the composite layer comprising filled pores, a dielectric layer (e.g., buried oxide), and a device layer. The structure can be used as initial substrate in fabricating radiofrequency chips. The resulting chips have suppressed parasitic effects, particularly, no induced conductive channel below the buried oxide.

8. 发明申请

US20170025306A1 METHODS FOR PREPARING LAYERED SEMICONDUCTOR STRUCTURES AND RELATED BONDED STRUCTURES 审中-公开
标题翻译：用于制备层状半导体结构和相关粘结结构的方法
公开(公告)号：US20170025306A1
公开(公告)日：2017-01-26
申请号：US15191975
申请日：2016-06-24
申请人： SunEdison Semiconductor Limited (UEN201334164H)
发明人： Gang Wang , Jeffrey L. Libbert , Qingmin Liu , Alex Usenko , Shawn George Thomas
IPC分类号： H01L21/762 , C30B29/06 , C30B1/02 , H01L21/02 , H01L29/06
CPC分类号： H01L21/76251 , H01L21/02532 , H01L21/02592 , H01L21/0262 , H01L21/02667
摘要： Methods for preparing silicon-on-insulator structures and related intermediate structures are disclosed. In some embodiments, a single crystal silicon seed crystal is bonded to an amorphous silicon layer disposed on a substrate and the amorphous layer is crystallized to form a monocrystalline silicon layer.
摘要翻译：公开了制备绝缘体上硅结构和相关中间结构的方法。在一些实施例中，将单晶硅晶种结合到设置在衬底上的非晶硅层，并且非晶层结晶以形成单晶硅层。

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