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1. 发明授权

US06551447B1 Inductive plasma reactor 有权
标题翻译：感应等离子体反应器
公开(公告)号：US06551447B1
公开(公告)日：2003-04-22
申请号：US09707368
申请日：2000-11-06
申请人： Stephen E. Savas , Brad S. Mattson , Martin L. Hammond , Steven C. Selbrede
发明人： Stephen E. Savas , Brad S. Mattson , Martin L. Hammond , Steven C. Selbrede
IPC分类号： H01L2100
CPC分类号： H01J37/32871 , H01J37/321 , H01J37/32357 , H01J37/32422 , H01J37/32706 , Y10S156/912
摘要： A plasma reactor and methods for processing semiconductor wafers are described. Gases are introduced into a reactor chamber. An induction coil surrounds the reactor chamber. RF power is applied to the induction coil and is inductively coupled into the reactor chamber causing a plasma to form. A split Faraday shield is interposed between the induction coil and the reactor chamber to substantially block the capacitive coupling of energy into the reactor chamber which may modulate the plasma potential. The configuration of the split Faraday shield may be selected to control the level of modulation of the plasma potential. For etch processes, a separate powered electrode may be used to accelerate ions toward a wafer surface. For isotropic etching processes, charged particles may be filtered from the gas flow, while a neutral activated species passes unimpeded to a wafer surface.
摘要翻译：描述了等离子体反应器和半导体晶片的处理方法。将气体引入反应室。感应线圈围绕反应室。 RF功率被施加到感应线圈并感应耦合到反应室中，形成等离子体。在感应线圈和反应室之间插入分裂的法拉第屏蔽，以基本上阻挡能量进入反应室的电容耦合，这可以调制等离子体电位。可以选择分裂法拉第屏蔽的配置来控制等离子体电位的调制水平。对于蚀刻工艺，可以使用单独的供电电极来将离子加速朝向晶片表面。对于各向同性蚀刻工艺，可以从气流中过滤带电粒子，而中性活性物质无阻碍地通过晶片表面。

2. 发明授权

US06355909B1 Method and apparatus for thermal processing of semiconductor substrates 有权
标题翻译：半导体衬底的热处理方法和装置
公开(公告)号：US06355909B1
公开(公告)日：2002-03-12
申请号：US09641461
申请日：2000-08-18
申请人： Stewart K. Griffiths , Robert H. Nilson , Brad S. Mattson , Stephen E. Savas
发明人： Stewart K. Griffiths , Robert H. Nilson , Brad S. Mattson , Stephen E. Savas
IPC分类号： F27D1100
CPC分类号： H01L21/67248 , C23C16/46 , C23C16/54 , C30B25/10 , C30B31/12 , H01L21/67109
摘要： An improved apparatus and method for thermal processing of semiconductor wafers. The apparatus and method provide the temperature stability and uniformity of a conventional batch furnace as well as the processing speed and reduced time-at-temperature of a lamp-heated rapid thermal processor (RTP). Individual wafers are rapidly inserted into and withdrawn from a furnace cavity held at a nearly constant and isothermal temperature. The speeds of insertion and withdrawal are sufficiently large to limit thermal stresses and thereby reduce or prevent plastic deformation of the wafer as it enters and leaves the furnace. By processing the semiconductor wafer in a substantially isothermal cavity, the wafer temperature and spatial uniformity of the wafer temperature can be ensured by measuring and controlling only temperatures of the cavity walls. Further, peak power requirements are very small compared to lamp-heated RTPs because the cavity temperature is not cycled and the thermal mass of the cavity is relatively large. Increased speeds of insertion and/or removal may also be used with non-isothermal furnaces.
摘要翻译：一种用于半导体晶片的热处理的改进的装置和方法。该设备和方法提供常规分批炉的温度稳定性和均匀性以及加热快速热处理器（RTP）的处理速度和降低的时间温度。将单个晶片快速插入并保持在几乎恒定和等温温度下的炉腔中。插入和退出的速度足够大以限制热应力，从而减少或防止晶片进入和离开炉时的塑性变形。通过在基本等温的空腔中处理半导体晶片，可以通过仅测量和控制空腔壁的温度来确保晶片温度的晶片温度和空间均匀性。此外，与灯加热的RTP相比，峰值功率要求非常小，因为腔温度不循环并且腔的热质量相对较大。插入和/或移除速度的增加也可以与非等温炉一起使用。

3. 发明授权

US6133550A Method and apparatus for thermal processing of semiconductor substrates 有权
公开(公告)号：US6133550A
公开(公告)日：2000-10-17
申请号：US140614
申请日：1998-08-26
申请人： Stewart K. Griffiths , Robert H. Nilson , Brad S. Mattson , Stephen E. Savas
发明人： Stewart K. Griffiths , Robert H. Nilson , Brad S. Mattson , Stephen E. Savas
IPC分类号： H01L21/677 , C23C16/46 , C23C16/54 , C30B25/10 , C30B31/12 , H01L21/00 , H01L21/205 , H01L21/26 , H01L21/265 , F27D11/00
CPC分类号： H01L21/67248 , C23C16/46 , C23C16/54 , C30B25/10 , C30B31/12 , H01L21/67109
摘要： An improved apparatus and method for thermal processing of semiconductor wafers. The apparatus and method provide the temperature stability and uniformity of a conventional batch furnace as well as the processing speed and reduced time-at-temperature of a lamp-heated rapid thermal processor (RTP). Individual wafers are rapidly inserted into and withdrawn from a furnace cavity held at a nearly constant and isothermal temperature. The speeds of insertion and withdrawal are sufficiently large to limit thermal stresses and thereby reduce or prevent plastic deformation of the wafer as it enters and leaves the furnace. By processing the semiconductor wafer in a substantially isothermal cavity, the wafer temperature and spatial uniformity of the wafer temperature can be ensured by measuring and controlling only temperatures of the cavity walls. Further, peak power requirements are very small compared to lamp-heated RTPs because the cavity temperature is not cycled and the thermal mass of the cavity is relatively large. Increased speeds of insertion and/or removal may also be used with non-isothermal furnaces.

4. 发明授权

US06342691B1 Apparatus and method for thermal processing of semiconductor substrates 失效
标题翻译：半导体衬底的热处理装置和方法
公开(公告)号：US06342691B1
公开(公告)日：2002-01-29
申请号：US09439833
申请日：1999-11-12
申请人： Kristian E. Johnsgard , Jean-François Daviet , James A. Givens , Stephen E. Savas , Brad S. Mattson , Ashur J. Atanos
发明人： Kristian E. Johnsgard , Jean-François Daviet , James A. Givens , Stephen E. Savas , Brad S. Mattson , Ashur J. Atanos
IPC分类号： F27B514
CPC分类号： H01L21/67115 , C30B31/12
摘要： A semiconductor substrate processing system and method of using a stable heating source with a large thermal mass relative to conventional lamp heating systems. The system dimensions and processing parameters are selected to provide a substantial heat flux to the substrate while reducing the potential of heat loss to the surrounding environment, particularly from the edges of the heat source and substrate. Aspects of the present invention include a dual resistive heater system comprising a base or primary heater, surrounded by a peripheral or edge heater. The impedance of the edge heater may be substantially matched to that of the primary heater such that a single power supply may be used to supply power to both heaters. Both resistive heaters deliver heat to a heated block, and the heaters and heated block are substantially enclosed within an insulated cavity. The walls of the insulated cavity may include multiple layers of insulation, and these layers may be substantially concentrically arranged. The innermost layers may comprise silicon carbide coated graphite; the outer layers may comprise opaque quartz. An embodiment of the invention includes a vacuum spool having a large conduction pathway for exhausting gases from the region of the chamber containing the resistive heaters, and a small conduction pathway for removing gases from other regions of the chamber. Temperature measurement sensors include thermocouples and optical pyrometers, with the advantage that a thermocouple may be used to calibrate an optical pyrometer in situ. An insulating shutter may be used to insulate the port through which substrates are inserted into the insulated and heated cavity. Support posts and gas injectors may include ports for optical pyrometers.
摘要翻译：相对于传统的灯加热系统，半导体衬底处理系统和使用具有大热质量的稳定的热源的方法。选择系统尺寸和处理参数以向基板提供实质的热通量，同时减少对周围环境，特别是从热源和基板的边缘的热损失的潜力。本发明的方面包括双电阻加热器系统，其包括被周边或边缘加热器包围的基座或主加热器。边缘加热器的阻抗可以与初级加热器的阻抗基本匹配，使得单个电源可以用于向两个加热器供电。两个电阻加热器将热量传递到加热块，并且加热器和加热块基本上封闭在绝缘腔内。绝缘腔的壁可以包括多层绝缘体，并且这些层可以基本上同心地布置。最内层可包括碳化硅涂覆的石墨; 外层可以包括不透明的石英。本发明的实施例包括具有用于从包含电阻加热器的室的区域排出气体的大的传导路径的真空阀芯，以及用于从腔室的其它区域去除气体的小的传导路径。温度测量传感器包括热电偶和光学高温计，其优点是热电偶可用于原位校准光学高温计。可以使用绝缘快门来将通过哪个基板插入绝缘和加热腔的端口绝缘。支撑柱和气体注入器可以包括用于光学高温计的端口。

5. 发明授权

US06143129A Inductive plasma reactor 失效
公开(公告)号：US06143129A
公开(公告)日：2000-11-07
申请号：US118281
申请日：1998-07-17
申请人： Stephen E. Savas , Brad S. Mattson , Martin L. Hammond , Steven C. Selbrede
发明人： Stephen E. Savas , Brad S. Mattson , Martin L. Hammond , Steven C. Selbrede
IPC分类号： H05H1/46 , C23C16/50 , C23F4/00 , H01J37/32 , H01L21/027 , H01L21/302 , H01L21/3065
CPC分类号： H01J37/32871 , H01J37/321 , H01J37/32357 , H01J37/32422 , H01J37/32706 , Y10S156/912
摘要： A plasma reactor and methods for processing semiconductor wafers are described. Gases are introduced into a reactor chamber. An induction coil surrounds the reactor chamber. RF power is applied to the induction coil and is inductively coupled into the reactor chamber causing a plasma to form. A split Faraday shield is interposed between the induction coil and the reactor chamber to substantially block the capacitive coupling of energy into the reactor chamber which may modulate the plasma potential. The configuration of the split Faraday shield may be selected to control the level of modulation of the plasma potential. For etch processes, a separate powered electrode may be used to accelerate ions toward a wafer surface. For isotropic etching processes, charged particles may be filtered from the gas flow, while a neutral activated species passes unimpeded to a wafer surface.

6. 发明授权

US5811022A Inductive plasma reactor 失效
公开(公告)号：US5811022A
公开(公告)日：1998-09-22
申请号：US340696
申请日：1994-11-15
申请人： Stephen E. Savas , Brad S. Mattson
发明人： Stephen E. Savas , Brad S. Mattson
IPC分类号： H05H1/46 , C23C16/50 , C23F4/00 , H01J37/32 , H01L21/027 , H01L21/302 , H01L21/3065 , H05H1/00
CPC分类号： H01J37/32871 , H01J37/321 , H01J37/32357 , H01J37/32422 , H01J37/32706 , Y10S156/912
摘要： A plasma reactor and methods for processing semiconductor wafers are described. Gases are introduced into a reactor chamber. An induction coil surrounds the reactor chamber. RF power is applied to the induction coil and is inductively coupled into the reactor chamber causing a plasma to form. A split Faraday shield is interposed between the induction coil and the reactor chamber to substantially block the capacitive coupling of energy into the reactor chamber which may modulate the plasma potential. The configuration of the split Faraday shield may be selected to control the level of modulation of the plasma potential. For etch processes, a separate powered electrode may be used to accelerate ions toward a wafer surface. For isotropic etching processes, charged particles may be filtered from the gas flow, while a neutral activated species passes unimpeded to a wafer surface.

7. 发明授权

US07534362B2 Uniform etching system and process for large rectangular substrates 失效
公开(公告)号：US07534362B2
公开(公告)日：2009-05-19
申请号：US11180294
申请日：2005-07-13
申请人： Stephen E. Savas
发明人： Stephen E. Savas
IPC分类号： B44C1/22 , C03C15/00 , C03C25/68 , C23F1/00
CPC分类号： H01J37/32082 , H01J37/3244
摘要： Apparatus and process for controlling etching of silicon-based or organic materials on large rectangular substrates for manufacture of flat panel displays or other devices. The disclosed etching process can remove silicon-based materials or organic polymers with a rate distribution such that all areas of the panel are finished at nearly the same time. It does so while minimizing electrical charging of the workpiece that could cause damage to the devices. The etching chamber employs a parallel plate RF discharge between two electrodes, one of which is the showerhead for gas introduction and the other supports the substrate to be processed. Reactant and other gases are provided to the discharge by a novel showerhead structure. The gases which provide reactants for etching silicon-based materials include halogenated compounds. Oxygen, water vapor or hydrogen with other gas additives may be used for etching organic polymers. The uniformity of etching across the substrate is controlled by adding other gas(es), including inert diluents, which can control the etching rate for either silicon-based materials or organic materials by accelerating and/or decreasing it. In addition, the distribution of the gases which are added can be varied to make the surface potential of the substrate more uniform. With a showerhead having a single reservoir that feeds all gases into the discharge, the gases may be added to the reservoir through multiple distribution structures within or adjacent to the reservoir. These structures are each supplied separately with the additive gases and, in turn, feed them to the different regions of the reservoir. The invention can thus provide different etching rates for different parts of the substrate, as may be required to finish film removal in all areas of the panel at nearly the same time. The invention also provides for chemical conversion of inorganic residues remaining after the oxidation of an organic polymer in the ashing process by addition of small amounts of halogenated gas(es) to the mixture flowing through the plasma sources. With the system and process of the invention, space efficiency, operating cost and capital cost for making large substrates can be reduced significantly.

8. 发明授权

US07232767B2 Slotted electrostatic shield modification for improved etch and CVD process uniformity 有权
标题翻译：开槽静电屏蔽改进，以改善蚀刻和CVD工艺均匀性
公开(公告)号：US07232767B2
公开(公告)日：2007-06-19
申请号：US10803453
申请日：2004-03-18
申请人： Rene George , Andreas Kadavanich , Daniel J. Devine , Stephen E. Savas , John Zajac , Hongching Shan
发明人： Rene George , Andreas Kadavanich , Daniel J. Devine , Stephen E. Savas , John Zajac , Hongching Shan
IPC分类号： H01L21/302
CPC分类号： H01L21/67069 , H01J37/321 , H01J37/32431 , H01L21/02104 , H01L21/3065 , H01L21/6715 , H05H1/46
摘要： A more uniform plasma process is implemented for treating a treatment object using an inductively coupled plasma source which produces an asymmetric plasma density pattern at the treatment surface using a slotted electrostatic shield having uniformly spaced-apart slots. The slotted electrostatic shield is modified in a way which compensates for the asymmetric plasma density pattern to provide a modified plasma density pattern at the treatment surface. A more uniform radial plasma process is described in which an electrostatic shield arrangement is configured to replace a given electrostatic shield in a way which provides for producing a modified radial variation characteristic across the treatment surface. The inductively coupled plasma source defines an axis of symmetry and the electrostatic shield arrangement is configured to include a shape that extends through a range of radii relative to the axis of symmetry.
摘要翻译：实施了更均匀的等离子体处理，以使用电感耦合等离子体源来处理处理对象，该等离子体源使用具有均匀间隔开的狭缝的开槽静电屏蔽件在处理表面处产生不对称等离子体密度图案。槽式静电屏蔽以补偿不对称等离子体密度图案的方式进行修改，以在处理表面提供改良的等离子体密度图案。描述了更均匀的径向等离子体处理，其中静电屏蔽装置被配置为以提供在整个处理表面上产生修改的径向变化特征的方式来替换给定的静电屏蔽。电感耦合等离子体源限定对称轴，并且静电屏蔽装置被配置为包括相对于对称轴延伸穿过半径范围的形状。

9. 发明授权

US06395641B2 Apparatus and method for pulsed plasma processing of a semiconductor substrate 有权
标题翻译：用于半导体衬底脉冲等离子体处理的装置和方法
公开(公告)号：US06395641B2
公开(公告)日：2002-05-28
申请号：US09860698
申请日：2001-05-16
申请人： Stephen E. Savas
发明人： Stephen E. Savas
IPC分类号： H01L2100
CPC分类号： H01J37/321 , H01J37/32082 , H01J37/32706 , H01J2237/004 , H01J2237/3345
摘要： Apparatus and method for an improved etch process. A power source alternates between high and low power cycles to produce and sustain a plasma discharge. Preferably, the high power cycles couple sufficient power into the plasma to produce a high density of ions (≳1011 cm−3) for etching. Preferably, the low power cycles allow electrons to cool off to reduce the average random (thermal) electron velocity in the plasma. Preferably, the low power cycle is limited in duration as necessary to prevent excessive plasma loss to the walls or due to recombination of negative and positive ions. It is an advantage of these and other aspects of the present invention that average electron thermal velocity is reduced, so fewer electrons overcome the plasma sheath and accumulate on substrate or mask layer surfaces. A separate power source alternates between high and low power cycles to accelerate ions toward the substrate being etched. In one embodiment, a strong bias is applied to the substrate in short bursts. Preferably, multiple burst occur during the average transit time for an ion to cross the plasma sheath and reach the substrate surface. Ions are pulsed toward the surface for etching. These ions are not deflected into sidewalls as readily as ions in conventional low energy etch processes due to reduced charge buildup and the relatively low duty cycle of power used to pulse ions toward the substrate surface.
摘要翻译：用于改进蚀刻工艺的装置和方法。电源在高功率和低功率周期之间交替产生和维持等离子体放电。优选地，高功率循环将足够的功率耦合到等离子体中以产生用于蚀刻的高密度离子（>〜1011cm-3）。优选地，低功率周期允许电子冷却以降低等离子体中的平均随机（热）电子速度。优选地，低功率循环的持续时间受到限制，以防止对壁的过度等离子体损失或由于负离子和正离子的复合。本发明的这些和其它方面的优点是平均电子热速度降低，因此较少的电子克服了等离子体鞘并积聚在衬底或掩模层表面上。单独的电源在高功率和低功率循环之间交替，以将离子加速朝向被蚀刻的衬底。在一个实施例中，以短脉冲串将强偏压施加到衬底。优选地，在平均通过时间期间发生多次爆发，以使离子穿过等离子体护套并到达衬底表面。离子脉冲朝表面进行蚀刻。这些离子由于电荷累积减少和脉冲离子朝向衬底表面的相对低的功率占空比而不会像传统的低能量蚀刻工艺中的离子一样容易地偏转到侧壁中。

10. 发明授权

US08236706B2 Method and apparatus for growing thin oxide films on silicon while minimizing impact on existing structures 有权
标题翻译：用于在硅上生长薄氧化膜同时最小化对现有结构的影响的方法和装置
公开(公告)号：US08236706B2
公开(公告)日：2012-08-07
申请号：US12334425
申请日：2008-12-12
申请人： Bruce W. Peuse , Yaozhi Hu , Paul Janis Timans , Guangcai Xing , Wilfried Lerch , Sing-Pin Tay , Stephen E. Savas , Georg Roters , Zsolt Nenyei , Ashok Sinha
发明人： Bruce W. Peuse , Yaozhi Hu , Paul Janis Timans , Guangcai Xing , Wilfried Lerch , Sing-Pin Tay , Stephen E. Savas , Georg Roters , Zsolt Nenyei , Ashok Sinha
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/31654 , H01L21/0223 , H01L21/02238 , H01L21/02323 , H01L21/0234 , H01L21/67115 , H01L21/67248 , H01L21/68771
摘要： Plasma assisted low temperature radical oxidation is described. The oxidation is selective to metals or metal oxides that may be present in addition to the silicon being oxidized. Selectivity is achieved by proper selection of process parameters, mainly the ratio of H2 to O2 gas. The process window may be enlarged by injecting H2O steam into the plasma, thereby enabling oxidation of silicon in the presence of TiN and W, at relatively low temperatures. Selective oxidation is improved by the use of an apparatus having remote plasma and flowing radicals onto the substrate, but blocking ions from reaching the substrate.
摘要翻译：描述了等离子体辅助低温自由基氧化。除了被氧化的硅之外，氧化对于可能存在的金属或金属氧化物是选择性的。选择性通过适当选择工艺参数来实现，主要是H2与O2气的比例。可以通过将H 2 O蒸汽注入到等离子体中来扩大工艺窗口，从而可以在相对低的温度下在TiN和W的存在下氧化硅。通过使用具有远离等离子体和流动基团的装置到衬底上但阻止离子到达衬底的装置来改善选择性氧化。

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