专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060209583A1 Method and apparatus for address allotting and verification in a semiconductor device 有权
标题翻译：用于半导体器件中的地址分配和验证的方法和装置
公开(公告)号：US20060209583A1
公开(公告)日：2006-09-21
申请号：US11341029
申请日：2006-01-27
申请人： Shozo Kawabata , Kenji Shibata , Takaaki Furuyama , Satoru Kawamoto
发明人： Shozo Kawabata , Kenji Shibata , Takaaki Furuyama , Satoru Kawamoto
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.
摘要翻译：半导体器件包括存储关于半导体器件的操作设置信息的CAM单元阵列，控制CAM单元阵列的读和写的控制器，行解码器和列解码器。利用这种结构，将不同的行地址分配给操作设置信息的各个功能。因此，在编程时，在未选择的功能的CAM单元阵列中不会引起应力。

2. 发明授权

US07433219B2 Method and apparatus for address allotting and verification in a semiconductor device 有权
标题翻译：用于半导体器件中的地址分配和验证的方法和装置
公开(公告)号：US07433219B2
公开(公告)日：2008-10-07
申请号：US11341029
申请日：2006-01-27
申请人： Shozo Kawabata , Kenji Shibata , Takaaki Furuyama , Satoru Kawamoto
发明人： Shozo Kawabata , Kenji Shibata , Takaaki Furuyama , Satoru Kawamoto
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.
摘要翻译：半导体器件包括存储关于半导体器件的操作设置信息的CAM单元阵列，控制CAM单元阵列的读和写的控制器，行解码器和列解码器。利用这种结构，将不同的行地址分配给操作设置信息的各个功能。因此，在编程时，在未选择的功能的CAM单元阵列中不会引起应力。

3. 发明授权

US07813154B2 Method and apparatus for address allotting and verification in a semiconductor device 有权
标题翻译：用于半导体器件中的地址分配和验证的方法和装置
公开(公告)号：US07813154B2
公开(公告)日：2010-10-12
申请号：US12199684
申请日：2008-08-27
申请人： Shozo Kawabata , Kenji Shibata , Takaaki Furuyama , Satoru Kawamoto
发明人： Shozo Kawabata , Kenji Shibata , Takaaki Furuyama , Satoru Kawamoto
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.
摘要翻译：半导体器件包括存储关于半导体器件的操作设置信息的CAM单元阵列，控制CAM单元阵列的读和写的控制器，行解码器和列解码器。利用这种结构，将不同的行地址分配给操作设置信息的各个功能。因此，在编程时，在未选择的功能的CAM单元阵列中不会引起应力。

4. 发明授权

US08023341B2 Method and apparatus for address allotting and verification in a semiconductor device 有权
标题翻译：用于半导体器件中的地址分配和验证的方法和装置
公开(公告)号：US08023341B2
公开(公告)日：2011-09-20
申请号：US12903065
申请日：2010-10-12
申请人： Shozo Kawabata , Kenji Shibata , Takaaki Furuyama , Satoru Kawamoto
发明人： Shozo Kawabata , Kenji Shibata , Takaaki Furuyama , Satoru Kawamoto
IPC分类号： G11C7/10
CPC分类号： G11C15/00
摘要： A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.
摘要翻译：半导体器件包括存储关于半导体器件的操作设置信息的CAM单元阵列，控制CAM单元阵列的读和写的控制器，行解码器和列解码器。利用这种结构，将不同的行地址分配给操作设置信息的各个功能。因此，在编程时，在未选择的功能的CAM单元阵列中不会引起应力。

5. 发明申请

US20080316787A1 METHOD AND APPARATUS FOR ADDRESS ALLOTTING AND VERIFICATION IN A SEMICONDUCTOR DEVICE 有权
标题翻译：用于在半导体器件中寻址和验证的方法和装置
公开(公告)号：US20080316787A1
公开(公告)日：2008-12-25
申请号：US12199684
申请日：2008-08-27
申请人： Shozo KAWABATA , Kenji Shibata , Takaaki Furuyama , Satoru Kawamoto
发明人： Shozo KAWABATA , Kenji Shibata , Takaaki Furuyama , Satoru Kawamoto
IPC分类号： G11C15/00 , G11C8/00
CPC分类号： G11C15/00
摘要： A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.
摘要翻译：半导体器件包括存储关于半导体器件的操作设置信息的CAM单元阵列，控制CAM单元阵列的读和写的控制器，行解码器和列解码器。利用这种结构，将不同的行地址分配给操作设置信息的各个功能。因此，在编程时，在未选择的功能的CAM单元阵列中不会引起应力。

6. 发明申请

US20060227629A1 Memory device and control method therefor 有权
标题翻译：存储器及其控制方法
公开(公告)号：US20060227629A1
公开(公告)日：2006-10-12
申请号：US11378444
申请日：2006-03-16
申请人： Koji Shimbayashi , Takaaki Furuyama , Kenji Shibata
发明人： Koji Shimbayashi , Takaaki Furuyama , Kenji Shibata
IPC分类号： G11C7/06
CPC分类号： G11C7/08 , G11C7/1018 , G11C16/26 , G11C16/32
摘要： An access identification circuit (4) identifies a first access operation or a second access operation and outputs an identification signal S. During the first access operation, stored data is read out after detecting a column address CADD, a burst address, and updating a word line to newly select memory cells MC. In the second access operation, the memory cells MC connected to the common word line which has been selected are selected by sequentially switching column selector switches. Operating condition information Dx (DAx and/or DBx) used for setting a load condition in a dummy load circuit (5) and/or setting a pulse width for an equalize signal EQ in an amplification control circuit (6) is stored in each of first and second storage sections (1, 2) that are provided for the first and second access operations, respectively. The operating condition information Dx is selected by a selector circuit (3) in response to the identification signal S and fed to the dummy load circuit (5) and/or the amplification control circuit (6). A suitable operating condition is selected for each of the access operations.
摘要翻译：访问识别电路（4）识别第一访问操作或第二访问操作并输出识别信号S.在第一访问操作期间，在检测列地址CADD，突发地址和更新字之后读出存储的数据行新选择存储单元MC。在第二访问操作中，通过依次切换列选择器开关来选择连接到所选择的公共字线的存储单元MC。在放大控制电路（6）中用于设置虚拟负载电路（5）中的负载条件和/或设定均衡信号EQ的脉冲宽度的工作条件信息Dx（DAx和/或DBx）被存储在分别为第一和第二存取操作提供的第一和第二存储部分（1,2）。操作条件信息Dx由选择器电路（3）响应于识别信号S选择并馈送到虚拟负载电路（5）和/或放大控制电路（6）。为每个访问操作选择合适的操作条件。

7. 发明授权

US07321515B2 Memory device and control method therefor 有权
标题翻译：存储器及其控制方法
公开(公告)号：US07321515B2
公开(公告)日：2008-01-22
申请号：US11378444
申请日：2006-03-16
申请人： Koji Shimbayashi , Takaaki Furuyama , Kenji Shibata
发明人： Koji Shimbayashi , Takaaki Furuyama , Kenji Shibata
IPC分类号： G11C7/00
CPC分类号： G11C7/08 , G11C7/1018 , G11C16/26 , G11C16/32
摘要： An access identification circuit (4) identifies a first access operation or a second access operation and outputs an identification signal S. During the first access operation, stored data is read out after detecting a column address CADD, a burst address, and updating a word line to newly select memory cells MC. In the second access operation, the memory cells MC connected to the common word line which has been selected are selected by sequentially switching column selector switches. Operating condition information Dx (DAx and/or DBx) used for setting a load condition in a dummy load circuit (5) and/or setting a pulse width for an equalize signal EQ in an amplification control circuit (6) is stored in each of first and second storage sections (1, 2) that are provided for the first and second access operations, respectively. The operating condition information Dx is selected by a selector circuit (3) in response to the identification signal S and fed to the dummy load circuit (5) and/or the amplification control circuit (6). A suitable operating condition is selected for each of the access operations.
摘要翻译：访问识别电路（4）识别第一访问操作或第二访问操作并输出识别信号S.在第一访问操作期间，在检测到列地址CADD，突发地址和更新单词之后读出存储的数据行新选择存储单元MC。在第二访问操作中，通过依次切换列选择器开关来选择连接到所选择的公共字线的存储单元MC。在放大控制电路（6）中用于设置虚拟负载电路（5）中的负载条件和/或设定均衡信号EQ的脉冲宽度的工作条件信息Dx（DAx和/或DBx）被存储在分别为第一和第二存取操作提供的第一和第二存储部分（1,2）。操作条件信息Dx由选择器电路（3）响应于识别信号S选择并馈送到虚拟负载电路（5）和/或放大控制电路（6）。为每个访问操作选择合适的操作条件。

8. 发明申请

US20050184767A1 Current-voltage converter circuit and its control method 有权
标题翻译：电流 - 电压转换电路及其控制方法
公开(公告)号：US20050184767A1
公开(公告)日：2005-08-25
申请号：US11061119
申请日：2005-02-18
申请人： Kenji Shibata , Satoru Kawamoto
发明人： Kenji Shibata , Satoru Kawamoto
IPC分类号： G11C16/26 , G11C16/28 , H03D1/00
CPC分类号： G11C16/28
摘要： An input current flowing into a current-voltage conversion circuit (1) is converted to a voltage value at an output terminal SAIN and, then, a differential amplification circuit (5) amplifies and outputs a differential voltage between the voltage value and the reference voltage Vref. PMOS and NMOS transistors T1, T2 are connected between the output terminal SAIN and the power-supply voltage VCC. After the output terminal SAIN is precharged to the power-supply voltage VCC by making the transistors conductive, the current-voltage conversion operation is performed by making a voltage drop corresponding to the input current. The precharge operation precharges the output terminal SAIN up to the power-supply voltage VCC and supplies precharge to a common data line N3 and bit lines.
摘要翻译：流入电流 - 电压转换电路（1）的输入电流被转换为输出端子SAIN处的电压值，然后差分放大电路（5）放大并输出电压值与基准电压之间的差分电压 Vref。 PMOS和NMOS晶体管T 1，T 2连接在输出端子SAIN和电源电压VCC之间。在通过使晶体管导通来将输出端子SAIN预充电到电源电压VCC之后，通过使与输入电流相对应的电压降来执行电流 - 电压转换操作。预充电操作将输出端子SAIN预充电到电源电压VCC，并将预充电提供给公共数据线N 3和位线。

9. 发明授权

US07046043B2 Current-voltage converter circuit and its control method 有权
标题翻译：电流 - 电压转换电路及其控制方法
公开(公告)号：US07046043B2
公开(公告)日：2006-05-16
申请号：US11061119
申请日：2005-02-18
申请人： Kenji Shibata , Satoru Kawamoto
发明人： Kenji Shibata , Satoru Kawamoto
IPC分类号： G01R19/00
CPC分类号： G11C16/28
摘要： An input current flowing into a current-voltage conversion circuit (1) is converted to a voltage value at an output terminal SAIN and, then, a differential amplification circuit (5) amplifies and outputs a differential voltage between the voltage value and the reference voltage Vref. PMOS and NMOS transistors T1, T2 are connected between the output terminal SAIN and the power-supply voltage VCC. After the output terminal SAIN is precharged to the power-supply voltage VCC by making the transistors conductive, the current-voltage conversion operation is performed by making a voltage drop corresponding to the input current. The precharge operation precharges the output terminal SAIN up to the power-supply voltage VCC and supplies precharge to a common data line N3 and bit lines.
摘要翻译：流入电流 - 电压转换电路（1）的输入电流被转换为输出端子SAIN处的电压值，然后差分放大电路（5）放大并输出电压值与基准电压之间的差分电压 Vref。 PMOS和NMOS晶体管T 1，T 2连接在输出端子SAIN和电源电压VCC之间。在通过使晶体管导通来将输出端子SAIN预充电到电源电压VCC之后，通过使与输入电流相对应的电压降来执行电流 - 电压转换操作。预充电操作将输出端子SAIN预充电到电源电压VCC，并将预充电提供给公共数据线N 3和位线。

10. 发明授权

US10137929B2 Electric power steering device for vehicle 有权
公开(公告)号：US10137929B2
公开(公告)日：2018-11-27
申请号：US14650706
申请日：2013-01-24
申请人： Kenichiro Aoki , Kenji Shibata , Takayoshi Tsujimoto
发明人： Kenichiro Aoki , Kenji Shibata , Takayoshi Tsujimoto
IPC分类号： B62D5/30 , B62D5/04
摘要： An electric power steering device for a vehicle includes a plurality of assist systems electromagnetically driving an electric motor. When a first or second assist system malfunctions, a malfunction state assist amount calculation part calculates an assist amount while decreasing a limit value at the vehicle stopping, to an amount smaller than a limit value at the vehicle moving. When a malfunction such as a disconnection or a fixing of the switching elements occurs in the first or second assist systems on the basis of a judgment result of a malfunction judgment function, an assist amount switching part supplies an assist amount received from the malfunction state assist amount calculation part to first and second motor drive control parts. When a malfunction occurs in one of the first and second assist systems, one of the first and second motor drive control parts drives the motor by using the assist amount.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式