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1. 发明授权

US07444255B2 System and method for analyzing lengths of branches of signal paths 失效
标题翻译：用于分析信号路径分支长度的系统和方法
公开(公告)号：US07444255B2
公开(公告)日：2008-10-28
申请号：US11768922
申请日：2007-06-27
申请人： Shou-Kuo Hsu , Chia-Nan Pai , Cheng-Shien Li
发明人： Shou-Kuo Hsu , Chia-Nan Pai , Cheng-Shien Li
IPC分类号： G01R27/28
CPC分类号： G06F17/5036 , G01R31/025 , G01R31/041
摘要： A system for analyzing lengths of branches of signal paths is disclosed. The system includes: a signal path naming module for naming all signal paths of a PCB; a signal path group selecting module for selecting a group of signal paths to be analyzed from the database; a signal path selecting module for selecting signal paths to be analyzed from the group of signal paths; a branch searching module for analyzing the selected signal paths, to search passive circuit components and external circuits connected to the selected signal paths for corresponding branches of the selected signal paths; a branch length calculating module for calculating a length of each branch; and a branch length comparing module for comparing each calculated branch length with a corresponding predefined maximal branch length to determine whether the calculated branch length is more than the predefined maximal branch length. A related method is also disclosed.
摘要翻译：公开了一种用于分析信号路径的分支长度的系统。该系统包括：用于命名PCB的所有信号路径的信号路径命名模块; 信号路径组选择模块，用于从数据库中选择要分析的一组信号路径; 信号路径选择模块，用于从信号路径组中选择要分析的信号路径; 用于分析所选择的信号路径的分支搜索模块，搜索与所选择的信号路径连接的无源电路组件和外部电路用于所选择的信号路径的相应分支; 分支长度计算模块，用于计算每个分支的长度; 以及分支长度比较模块，用于将每个计算的分支长度与相应的预定义的最大分支长度进行比较，以确定所计算的分支长度是否大于预定的最大分支长度。还公开了相关方法。

2. 发明授权

US08438529B1 Computing device and method for checking signal transmission line 失效
标题翻译：检测信号传输线的计算装置及方法
公开(公告)号：US08438529B1
公开(公告)日：2013-05-07
申请号：US13585854
申请日：2012-08-15
申请人： Ya-Ling Huang , Ling-Ling Shen , Chia-Nan Pai , Shou-Kuo Hsu
发明人： Ya-Ling Huang , Ling-Ling Shen , Chia-Nan Pai , Shou-Kuo Hsu
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A computer-based method and a computing device for checking signal transmission lines of a printed circuit board (PCB) layout are provided. The computing device identifies differential pairs in a currently run PCB layout according to an information file for the currently run PCB layout, checks whether any signal transmission line is routed between switching vias of each differential pair according to the information file for the currently run PCB layout, and displays a routing error window to display information of each misrouted signal transmission line.
摘要翻译：提供了一种用于检查印刷电路板（PCB）布局的信号传输线的基于计算机的方法和计算装置。根据当前运行的PCB布局的信息文件，计算设备根据当前运行的PCB布局的信息文件识别当前运行的PCB布局中的差分对，根据当前运行的PCB布局的信息文件，检查每个差分对的切换通孔之间是否有任何信号传输线路由，并显示路由错误窗口以显示每条错误路由的信号传输线路的信息。

3. 发明授权

US08146048B2 System and method for removing T-point elements with unused stubs from a PCB layout design 失效
标题翻译：用于从PCB布局设计中删除未使用短截线的T点元素的系统和方法
公开(公告)号：US08146048B2
公开(公告)日：2012-03-27
申请号：US12699839
申请日：2010-02-03
申请人： Han-Long Chen , Chia-Nan Pai , Shou-Kuo Hsu
发明人： Han-Long Chen , Chia-Nan Pai , Shou-Kuo Hsu
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A system and method for removing T-point elements with unused stubs from a printed circuit board (PCB) layout design obtains each signal line including one or more T-point elements in the PCB layout design, divides the obtained signal line into a plurality of lines according to the one or more T-point elements with unused stubs, and obtains properties of each of the plurality of lines. The system and method further deletes the original layout of the signal line and reconnects the plurality of lines according to the properties of each of the plurality of lines to generate a reconnected signal line, and outputs the reconnected signal line on a display device.
摘要翻译：用于从印刷电路板（PCB）布局设计中去除具有未使用的短截线的T点元件的系统和方法获得在PCB布局设计中包括一个或多个T点元件的每条信号线，将获得的信号线分成多个根据具有未使用短截线的一个或多个T点元素的线，并且获得多条线中的每一条的属性。该系统和方法进一步删除信号线的原始布局，并根据多条线中的每条线路的属性重新连接多条线路，以产生重新连接的信号线，并将重新连接的信号线输出到显示设备上。

4. 发明授权

US07843281B2 Circuit topology for multiple loads 有权
标题翻译：多个负载的电路拓扑
公开(公告)号：US07843281B2
公开(公告)日：2010-11-30
申请号：US11838238
申请日：2007-08-14
申请人： Shou-Kuo Hsu , Chia-Nan Pai , Hsiao-Chuan Tu
发明人： Shou-Kuo Hsu , Chia-Nan Pai , Hsiao-Chuan Tu
IPC分类号： H03H7/38
CPC分类号： H05K1/0246 , H05K1/0237 , H05K2201/09254 , H05K2201/10022
摘要： A circuit topology for multiple loads is provided. In an embodiment, the circuit topology includes a driving terminal (50), a first node (A), a first receiving terminal (10), and a second receiving terminal (20). The driving terminal is coupled to the first node via a main transmission line (11), the first node is respectively coupled to the first and second receiving terminals via a first branch transmission line (13) and a second branch transmission line (12). A first resistor (R2) is mounted on the second branch transmission line, a distance the signal travels from the driving terminal to the second receiving terminal via the main transmission line and the second branch transmission line is greater than a distance the signal travels from the driving terminal to the first receiving terminal via the main transmission and the first branch transmission line.
摘要翻译：提供了多个负载的电路拓扑。在一个实施例中，电路拓扑包括驱动终端（50），第一节点（A），第一接收终端（10）和第二接收终端（20）。驱动终端经由主传输线（11）耦合到第一节点，第一节点经由第一分支传输线（13）和第二分支传输线（12）分别耦合到第一和第二接收终端。第一电阻器（R2）安装在第二分支传输线上，信号经由主传输线从驱动端到第二接收端的距离，第二分支传输线大于信号从驱动终端通过主传输和第一分支传输线路连接到第一接收终端。

5. 发明授权

US08441327B2 Printed circuit board 有权
标题翻译：印刷电路板
公开(公告)号：US08441327B2
公开(公告)日：2013-05-14
申请号：US12960321
申请日：2010-12-03
申请人： Hua-Li Zhou , Ming Wei , Chia-Nan Pai , Shou-Kuo Hsu
发明人： Hua-Li Zhou , Ming Wei , Chia-Nan Pai , Shou-Kuo Hsu
IPC分类号： H03H7/38
CPC分类号： H05K1/0245 , H05K2201/09727
摘要： A printed circuit board includes an insulation layer and a signal layer attached to the insulation layer. The signal layer includes a pair of differential transmission lines. Width W of each of the differential transmission lines is changed according to change of space S between the differential transmission lines, based on the following formula: W = C ⁢ ⁢ 1 × H × ( C ⁢ ⁢ 2 × H 0.8 ⁢ W 0 + T ) C ⁢ ⁢ 3 × ⅇ C ⁢ ⁢ 4 × S 0 H - 1 1 - C ⁢ ⁢ 3 × ⅇ C ⁢ ⁢ 4 × S H - 1.25 ⁢ T In above formula, C1=7.475, C2=5.98, C3=0.48, C4=−0.96, H is a thickness of the insulation layer, W0 is an original width of each of the differential transmission lines, and S0 is an original space between the differential transmission lines, and T is a thickness of each of the differential transmission lines.
摘要翻译：印刷电路板包括绝缘层和附着到绝缘层的信号层。信号层包括一对差动传输线。差分传输线路的宽度W根据以下公式根据差分传输线路之间的空间S的变化而变化：W = C⁢1×H×（Cé2×H 0.8W 0 + T）C uch 3×ⅇC ud 4×S 0 H-1 1 -C⁢3×ⅇC ud 4×SH-1.25T在上式中，C1 = 7.475，C2 = 5.98，C3 = 0.48，C4 = -0.96，H是绝缘层的厚度，W0是差分传输线的原始宽度，S0是差动传输线之间的原始空间，T是各个差分传输线的厚度差动传输线。

6. 发明授权

US08402423B2 System and method for verifying PCB layout 失效
标题翻译：验证PCB布局的系统和方法
公开(公告)号：US08402423B2
公开(公告)日：2013-03-19
申请号：US13244625
申请日：2011-09-25
申请人： Zheng Shan , Shi-Piao Luo , Chia-Nan Pai , Shou-Kuo Hsu
发明人： Zheng Shan , Shi-Piao Luo , Chia-Nan Pai , Shou-Kuo Hsu
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5077
摘要： In a method for verifying a printed circuit board (PCB) layout using a computing device, a PCB simulation file is obtained from a storage device of the computing device, and a PCB image is displayed on a display device according to the PCB simulation file. The PCB image includes multiple signal lines and switching voltage regulator nodes (SVRN). A SVRN to be checked is selected from the PCB image, and all signal lines around the SVRN are searched. The method calculates a layout distance between the selected SVRN and each of the searched signal lines, and generates a graphical window interface to position a signal line whose layout distance is equal to or less than the minimum distance. The method further modifies the layout of the positioned signal line to satisfy a layout design specification by increasing the layout distance to the minimum distance.
摘要翻译：在使用计算装置验证印刷电路板（PCB）布局的方法中，从计算装置的存储装置获得PCB模拟文件，并且根据PCB仿真文件在显示装置上显示PCB图像。 PCB图像包括多个信号线和开关电压调节器节点（SVRN）。从PCB图像中选择要检查的SVRN，并搜索SVRN周围的所有信号线。该方法计算所选择的SVRN与所搜索的信号线之间的布局距离，并且生成图形窗口界面以定位其布局距离等于或小于最小距离的信号线。该方法通过将布局距离增加到最小距离来进一步修改定位信号线的布局以满足布局设计规范。

7. 发明授权

US08247704B2 Motherboard interconnection device 有权
标题翻译：主板互连设备
公开(公告)号：US08247704B2
公开(公告)日：2012-08-21
申请号：US12503680
申请日：2009-07-15
申请人： Chia-Nan Pai , Han-Long Chen , Ning Li , Shou-Kuo Hsu
发明人： Chia-Nan Pai , Han-Long Chen , Ning Li , Shou-Kuo Hsu
IPC分类号： H05K1/18 , H05K3/30
CPC分类号： H05K1/0239 , H05K1/0245 , H05K1/0295 , H05K1/113 , H05K3/429 , H05K2201/044 , H05K2201/09254 , H05K2201/10015 , H05K2201/10545 , H05K2201/10636 , Y02P70/611 , Y10T29/4913
摘要： A motherboard interconnection device includes a top layer, a bottom layer, a first and a third electronic elements positioned on the top layer, and a second and a fourth electronic elements positioned on the bottom layer. A first end of the first electronic element on the top layer is connected to the first end of the second electronic element on the bottom layer with a first via hole, and the first end of the third electronic element on the top layer is connected to the first end of the fourth electronic element on the bottom layer with a second via hole. The second ends of the two electronic elements on the top layer are connected to a first part, and the second ends of the two electronic elements on the bottom layer are connected to a second part.
摘要翻译：母板互连装置包括顶层，底层，位于顶层上的第一和第三电子元件以及位于底层上的第二和第四电子元件。顶层上的第一电子元件的第一端通过第一通孔连接到底层上的第二电子元件的第一端，并且顶层上的第三电子元件的第一端连接到第四电子元件的第一端部具有第二通孔。顶层上的两个电子元件的第二端连接到第一部分，底层上的两个电子元件的第二端连接到第二部分。

8. 发明授权

US08194412B2 Printed circuit board 有权
标题翻译：印刷电路板
公开(公告)号：US08194412B2
公开(公告)日：2012-06-05
申请号：US12647395
申请日：2009-12-25
申请人： Hua-Li Zhou , Chia-Nan Pai , Shou-Kuo Hsu
发明人： Hua-Li Zhou , Chia-Nan Pai , Shou-Kuo Hsu
IPC分类号： H05K1/18 , H05K1/16 , H05K7/00
CPC分类号： H05K1/0253 , H05K1/181 , H05K2201/09381 , H05K2201/0969 , H05K2201/10015 , H05K2201/10022 , H05K2201/10636 , Y02P70/611
摘要： A printed circuit board includes a signal plane and a reference plane. The signal plane includes a pad, a passive element mounted on the pad, and a signal transmission line electrically connected to the passive element via the pad. The reference plane provides a return path for a signal transmitted through the passive element and the signal transmission line. A void is defined in the reference plane corresponding to the passive element, to increase a length of the return path. A length of a first axis, perpendicular to the signal transmission line, of the void satisfies a following equation: W 1 ≈ 8 ⁢ Wpad + 10 ⁢ T 0.8 ⁢ Wtrace + T , wherein Wpad is a width of the pad, Wtrace is a width of the transmission line, T is the height of the pad.
摘要翻译：印刷电路板包括信号平面和参考平面。信号平面包括焊盘，安装在焊盘上的无源元件以及通过焊盘与无源元件电连接的信号传输线。参考平面为通过无源元件和信号传输线传输的信号提供返回路径。在对应于无源元件的参考平面中定义空隙，以增加返回路径的长度。垂直于信号传输线的第一轴的长度满足以下等式：W 1≈8Wpad+ 10T 0.8Wtrace + T，其中Wpad是焊盘的宽度，Wtrace是传输线的宽度，T是焊盘的高度。

9. 发明授权

US08058557B2 Printed circuit board 失效
标题翻译：印刷电路板
公开(公告)号：US08058557B2
公开(公告)日：2011-11-15
申请号：US11957416
申请日：2007-12-15
申请人： Chien-Hung Liu , Shou-Kuo Hsu , Chia-Nan Pai
发明人： Chien-Hung Liu , Shou-Kuo Hsu , Chia-Nan Pai
IPC分类号： H05K1/00
CPC分类号： H05K1/0245 , H05K2201/0715 , H05K2201/09236 , H05K2201/09672
摘要： An exemplary PCB includes a first reference layer, a first signal layer, a second signal layer, and a third signal layer in that order, a first differential pair is arranged in the first signal layer in edge-coupled structure and references the first reference layer, a distance between the first signal layer and the second signal layer is greater than a distance between the first reference layer and the first signal layer, a second differential pair is arranged in the second signal layer and the third signal layer in broad-coupled structure. The PCB has a high density layout of transmission lines.
摘要翻译：示例性PCB包括第一参考层，第一信号层，第二信号层和第三信号层，第一差分对以边缘耦合结构布置在第一信号层中，并参考第一参考层第一信号层和第二信号层之间的距离大于第一参考层和第一信号层之间的距离，第二差分对被布置在第二信号层中，第三信号层以广泛耦合结构。 PCB具有传输线高密度布局。

10. 发明授权

US08604351B2 Printed circuit board with circuit topology 失效
标题翻译：带电路拓扑的印刷电路板
公开(公告)号：US08604351B2
公开(公告)日：2013-12-10
申请号：US13335996
申请日：2011-12-23
申请人： Hua-Li Zhou , Chia-Nan Pai , Shou-Kuo Hsu
发明人： Hua-Li Zhou , Chia-Nan Pai , Shou-Kuo Hsu
IPC分类号： H05K1/09
CPC分类号： H05K1/0253
摘要： A printed circuit board includes a signal layer and a reference layer. The signal layer is covered with copper foil. A circuit topology for multiple loads is set on the signal layer. The circuit topology includes a driving terminal, a first signal receiving terminal, and a second signal receiving terminal. The driving terminal is connected to a node through a first transmission line. The node is connected to the first and second signal receiving terminals respectively through a second and a third transmission lines. A difference between lengths of the second and third transmission lines is greater than a product of a transmission speed and a rise time of signals from the driving terminal. The reference layer is covered with copper foil, and arranged under the signal layer. A region without copper foil is formed on the reference layer, under the second transmission line.
摘要翻译：印刷电路板包括信号层和参考层。信号层被铜箔覆盖。在信号层上设置多个负载的电路拓扑。电路拓扑包括驱动端子，第一信号接收端子和第二信号接收端子。驱动终端通过第一传输线连接到节点。节点分别通过第二和第三传输线连接到第一和第二信号接收终端。第二和第三传输线的长度之差大于来自驱动终端的信号的传输速度和上升时间的乘积。参考层用铜箔覆盖，并布置在信号层下面。在第二传输线下方，在参考层上形成没有铜箔的区域。

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