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    • 3. 发明授权
    • System for detecting access to storage
    • 用于检测存储访问的系统
    • US4641277A
    • 1987-02-03
    • US550199
    • 1983-11-09
    • Kiyoshi YataHideo Sawada
    • Kiyoshi YataHideo Sawada
    • G06F11/34G06F11/36G06F12/10G06F9/00
    • G06F11/3636G06F11/34G06F12/1027
    • A system for detecting access to a storage in a data processing apparatus which includes an address translation look-aside buffer which holds a part of an address translation table listing correspondences between logical addresses and real addresses, entry of the translation look-aside buffer being referred to upon every access to the storage. Each of the entries is added with information bit indicating whether a storage region corresponding to a given entry includes an area which is allocated for the detection of the access to the storage. Detection as to whether an address for accessing the storage is located within the area allocated for the access detection is not carried out when the identification information indicates that the storage region to be accessed does not include the area allocated for the access detection.
    • 一种用于检测对数据处理设备中的存储器的访问的系统,该系统包括地址转换后备缓冲器,其存储列出逻辑地址和实际地址之间的对应关系的地址转换表的一部分,所述翻译后备缓冲器的入口被引用 每次访问存储。 添加每个条目,其中指示与给定条目相对应的存储区域是否包括被分配用于检测对存储器的访问的区域的信息位。 当识别信息指示要访问的存储区域不包括为访问检测分配的区域时,不执行用于访问存储器的地址是否位于为访问检测分配的区域内的检测。
    • 4. 发明授权
    • Data processing apparatus for virtual memory system
    • 虚拟内存系统数据处理装置
    • US4628451A
    • 1986-12-09
    • US462120
    • 1983-01-28
    • Hideo SawadaKiyoshi Yata
    • Hideo SawadaKiyoshi Yata
    • G06F12/04G06F12/10G06F9/34
    • G06F12/1027G06F12/04
    • A data processing apparatus for a virtual memory system including a logical address register, a real address register, a paged address translation table and an address translation buffer in which a map of a fraction of the paged address translation table is stored columnwise. Upon checking address translatability of a logical address into a real address, a bit of a translation control word contained in the column of the address translation buffer relevant to that logical address indicates whether or not a succeeding logical address is susceptible to the address translation. Necessity to pretest the address translatability of every logical address is obviated. System overhead is considerably reduced.
    • 一种用于虚拟存储器系统的数据处理装置,包括逻辑地址寄存器,实地址寄存器,分页地址转换表和地址转换缓冲器,其中分页地址转换表的一部分的映射被分列存储。 在将逻辑地址的地址可译性检查到实际地址中时,包含在与该逻辑地址相关的地址转换缓冲器的列中的翻译控制字的位指示后续逻辑地址是否容易进行地址转换。 预测每个逻辑地址的地址可译性的必要性被消除。 系统开销显着降低。