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1. 发明申请

US20110140196A1 EMBEDDED BIT LINE STRUCTURE, FIELD EFFECT TRANSISTOR STRUCTURE WITH THE SAME AND METHOD OF FABRICATING THE SAME 有权
标题翻译：嵌入式位线结构，场效应晶体管结构及其制作方法
公开(公告)号：US20110140196A1
公开(公告)日：2011-06-16
申请号：US12635662
申请日：2009-12-10
申请人： Shing-Hwa Renn , Cheng-Chih Huang , Yung-Meng Huang
发明人： Shing-Hwa Renn , Cheng-Chih Huang , Yung-Meng Huang
IPC分类号： H01L29/78 , H01L29/06 , H01L21/336
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10826 , H01L27/10879 , H01L27/10885
摘要： An embedded bit line structure, in which, a substrate includes an insulator layer having an original top surface and a semiconductor layer on the original top surface of the insulator layer, and a bit line is disposed within the lower portion of the trench along one side of an active area. The bit line includes a first portion and a second portion. The first portion is located within the insulator layer and below the original top surface of the insulator layer. The second portion is disposed on the first portion to electrically connect the semiconductor layer of the active area. An insulator liner is disposed on the first portion of the bit line and between the second portion of the bit line and the semiconductor layer of the substrate opposite the active area for isolation. An STI is disposed within the trench to surround the active area for isolation.
摘要翻译：一种嵌入式位线结构，其中，衬底包括具有原始顶表面的绝缘体层和在绝缘体层的原始顶表面上的半导体层，并且位线沿着一侧设置在沟槽的下部的活跃区域。位线包括第一部分和第二部分。第一部分位于绝缘体层内并且位于绝缘体层的原始顶表面下方。第二部分设置在第一部分上以电连接有源区的半导体层。绝缘体衬垫设置在位线的第一部分上，位于位线的第二部分与衬底的半导体层之间，与激活区域相反以进行隔离。 STI设置在沟槽内以围绕有源区域进行隔离。

2. 发明授权

US07948027B1 Embedded bit line structure, field effect transistor structure with the same and method of fabricating the same 有权
标题翻译：嵌入式位线结构，场效应晶体管结构相同，制造方法相同
公开(公告)号：US07948027B1
公开(公告)日：2011-05-24
申请号：US12635662
申请日：2009-12-10
申请人： Shing-Hwa Renn , Cheng-Chih Huang , Yung-Meng Huang
发明人： Shing-Hwa Renn , Cheng-Chih Huang , Yung-Meng Huang
IPC分类号： H01L29/76
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10826 , H01L27/10879 , H01L27/10885
摘要： An embedded bit line structure, in which, a substrate includes an insulator layer having an original top surface and a semiconductor layer on the original top surface of the insulator layer, and a bit line is disposed within the lower portion of the trench along one side of an active area. The bit line includes a first portion and a second portion. The first portion is located within the insulator layer and below the original top surface of the insulator layer. The second portion is disposed on the first portion to electrically connect the semiconductor layer of the active area. An insulator liner is disposed on the first portion of the bit line and between the second portion of the bit line and the semiconductor layer of the substrate opposite the active area for isolation. An STI is disposed within the trench to surround the active area for isolation.
摘要翻译：一种嵌入式位线结构，其中，衬底包括具有原始顶表面的绝缘体层和在绝缘体层的原始顶表面上的半导体层，并且位线沿着一侧设置在沟槽的下部的活跃区域。位线包括第一部分和第二部分。第一部分位于绝缘体层内并且位于绝缘体层的原始顶表面下方。第二部分设置在第一部分上以电连接有源区的半导体层。绝缘体衬垫设置在位线的第一部分上，位于位线的第二部分与衬底的半导体层之间，与激活区域相反以进行隔离。 STI设置在沟槽内以围绕有源区域进行隔离。

3. 发明授权

US07476923B2 Memory device and fabrication thereof 有权
标题翻译：存储器件及其制造
公开(公告)号：US07476923B2
公开(公告)日：2009-01-13
申请号：US11297237
申请日：2005-12-07
申请人： Cheng-Chih Huang
发明人： Cheng-Chih Huang
IPC分类号： H01L29/94
CPC分类号： H01L27/10841 , H01L27/10867 , H01L29/945
摘要： A semiconductor memory device. A trench capacitor disposed at a lower portion of a trench in a substrate, in which the trench capacitor comprises a filling electrode layer and a collar dielectric layer surrounding the filling electrode layer. The top of the collar dielectric layer is lower than top surface level of the filling electrode layer. A vertical transistor is disposed at the upper portion of the trench, comprising a doped region disposed in a portion of the trench adjacent to the trench. A buried conductive layer interposed between the vertical transistor and the trench capacitor, wherein the cross section of the buried conductive layer is H shaped. The trench capacitor and the doping region of vertical transistor are electrically connected through the H shaped buried conductive layer.
摘要翻译：半导体存储器件。沟槽电容器，设置在衬底的沟槽的下部，沟槽电容器包括填充电极层和围绕填充电极层的套环电介质层。轴环电介质层的顶部低于填充电极层的顶表面水平。垂直晶体管设置在沟槽的上部，包括设置在与沟槽相邻的沟槽的一部分中的掺杂区域。插入在垂直晶体管和沟槽电容器之间的埋入导电层，其中掩埋导电层的横截面为H形。沟槽电容器和垂直晶体管的掺杂区域通过H形掩埋导电层电连接。

4. 发明申请

US20060270144A1 Memory cells with vertical transistor and capacitor and fabrication methods thereof 有权
标题翻译：具有垂直晶体管和电容器的存储单元及其制造方法
公开(公告)号：US20060270144A1
公开(公告)日：2006-11-30
申请号：US11499348
申请日：2006-08-03
申请人： Cheng-Chih Huang
发明人： Cheng-Chih Huang
IPC分类号： H01L21/8244 , H01L29/00
CPC分类号： H01L27/10876 , H01L27/10841
摘要： Memory cells with vertical transistor and capacitor and fabrication methods thereof. The memory cell comprises a substrate with a trench. A capacitor is disposed at the bottom of the trench. A first conductive layer is electrically coupled to the capacitor. The first conductive layer is isolated the substrate by a collar dielectric layer. A trench top oxide (TTO) layer is disposed on the first conductive layer. A vertical transistor is disposed over the TTO layer. The vertical transistor comprises a gate dielectric layer disposed on the sidewalls of the upper portion of the trench, and a metal gate disposed in the upper portion of the trench.
摘要翻译：具有垂直晶体管和电容器的存储单元及其制造方法。存储单元包括具有沟槽的衬底。电容器设置在沟槽的底部。第一导电层电耦合到电容器。第一导电层通过套环电介质层隔离衬底。沟槽顶部氧化物（TTO）层设置在第一导电层上。垂直晶体管设置在TTO层上。垂直晶体管包括设置在沟槽上部侧壁上的栅介电层和设置在沟槽上部的金属栅极。

5. 发明授权

US07078748B2 Multi-layer gate stack structure comprising a metal layer for a FET device, and method for fabricating the same 失效
标题翻译：包括用于FET器件的金属层的多层栅极堆栈结构及其制造方法
公开(公告)号：US07078748B2
公开(公告)日：2006-07-18
申请号：US10865763
申请日：2004-06-14
申请人： Matthias Goldbach , Frank Jakubowski , Ralf Koepe , Chao-Wen Lay , Kristin Schupke , Michael Schmidt , Cheng-Chih Huang
发明人： Matthias Goldbach , Frank Jakubowski , Ralf Koepe , Chao-Wen Lay , Kristin Schupke , Michael Schmidt , Cheng-Chih Huang
IPC分类号： H01L27/148
CPC分类号： H01L21/28044
摘要： A multi-layer gate stack structure of a field-effect transistor device is fabricated by providing a gate electrode layer stack with a polysilicon layer, a transition metal interface layer, a nitride barrier layer and then a metal layer on a gate dielectric, wherein the transition metal is titanium, tantalum or cobalt. Patterning the gate electrode layer stack comprises a step of patterning the metal layer and the barrier layer with an etch stop on the surface of the interface layer. Exposed portions of the interface layer are removed and the remaining portions are pulled back from the sidewalls of the gate stack structure leaving divots extending along the sidewalls of the gate stack structure between the barrier layer and the polysilicon layer. A nitride liner encapsulating the metal layer, the barrier layer and the interface layer fills the divots left by the pulled-back interface layer. The nitride liner is opened before the polysilicon layer is patterned. As the requirement for an overetch into the polysilicon layer during the etch of the metal layer, the barrier layer and the interface layer is omitted, the height of the polysilicon layer can be reduced. The aspect ration of the gate stack structure is improved, the feasibility of pattern and fill processes enhanced and the range of an angle under which implants can be performed is extended.
摘要翻译：通过提供具有多晶硅层，过渡金属界面层，氮化物阻挡层，然后在栅极电介质上的金属层的栅电极层堆叠来制造场效应晶体管器件的多层栅极堆叠结构，其中，过渡金属是钛，钽或钴。对栅电极层堆叠进行图案化包括在界面层的表面上用蚀刻阻挡层图案化金属层和阻挡层的步骤。界面层的暴露部分被去除，其余的部分从栅极叠层结构的侧壁被拉回，留下在阻挡层和多晶硅层之间的栅堆叠结构的侧壁延伸的纹理。封装金属层，阻挡层和界面层的氮化物衬垫填充由拉回界面层留下的凹坑。在将多晶硅层图案化之前打开氮化物衬垫。作为在金属层的蚀刻期间进行多晶硅层的蚀刻的要求，省略了阻挡层和界面层，可以降低多晶硅层的高度。提高了栅极堆叠结构的方面，增加了图案和填充过程的可行性，并且延长了可以进行植入的角度范围。

6. 发明授权

US06773993B2 Method for manufacturing a self-aligned split-gate flash memory cell 有权
公开(公告)号：US06773993B2
公开(公告)日：2004-08-10
申请号：US09880783
申请日：2001-06-15
申请人： Chi-Hui Lin , Chung-Lin Huang , Cheng-Chih Huang
发明人： Chi-Hui Lin , Chung-Lin Huang , Cheng-Chih Huang
IPC分类号： H01L21336
CPC分类号： H01L29/42332 , H01L21/28273
摘要： A method for manufacturing a split-gate flash memory cell, comprising the steps of forming an active region on a semiconductor substrate; forming a buffer layer on the semiconductor substrate; forming a first dielectric layer on the buffer layer; removing part of the first dielectric layer; defining an opening; removing the buffer layer within the opening; forming a gate insulating layer and floating gates; forming a source region in the semiconductor substrate; depositing a conformal second dielectric layer on the opening; removing the buffer layer outside the first dielectric layer and the floating gates; and forming an oxide layer and control gates.

7. 发明授权

US07445986B2 Memory cells with vertical transistor and capacitor and fabrication methods thereof 有权
标题翻译：具有垂直晶体管和电容器的存储单元及其制造方法
公开(公告)号：US07445986B2
公开(公告)日：2008-11-04
申请号：US11499348
申请日：2006-08-03
申请人： Cheng-Chih Huang
发明人： Cheng-Chih Huang
IPC分类号： H01L21/8242
CPC分类号： H01L27/10876 , H01L27/10841
摘要： Memory cells with vertical transistor and capacitor and fabrication methods thereof. The memory cell comprises a substrate with a trench. A capacitor is disposed at the bottom of the trench. A first conductive layer is electrically coupled to the capacitor. The first conductive layer is isolated the substrate by a collar dielectric layer. A trench top oxide (TTO) layer is disposed on the first conductive layer. A vertical transistor is disposed over the TTO layer. The vertical transistor comprises a gate dielectric layer disposed on the sidewalls of the upper portion of the trench, and a metal gate disposed in the upper portion of the trench.
摘要翻译：具有垂直晶体管和电容器的存储单元及其制造方法。存储单元包括具有沟槽的衬底。电容器设置在沟槽的底部。第一导电层电耦合到电容器。第一导电层通过套环电介质层隔离衬底。沟槽顶部氧化物（TTO）层设置在第一导电层上。垂直晶体管设置在TTO层上。垂直晶体管包括设置在沟槽上部侧壁上的栅介电层和设置在沟槽上部的金属栅极。

8. 发明申请

US20050064643A1 Method for isolation layer for a vertical DRAM 有权
标题翻译：垂直DRAM隔离层方法
公开(公告)号：US20050064643A1
公开(公告)日：2005-03-24
申请号：US10943699
申请日：2004-09-17
申请人： Cheng-Chih Huang , Sheng-Wei Yang , Chen-Chou Huang , Sheng-Tsung Chen
发明人： Cheng-Chih Huang , Sheng-Wei Yang , Chen-Chou Huang , Sheng-Tsung Chen
IPC分类号： H01L21/8238 , H01L21/8242
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10876
摘要： A method for forming isolation layer in a vertical DRAM. A semiconductor substrate with a plurality of first trenches is provided, with a collar dielectric layer is formed on a sidewall of each, and each filled with a first conducting layer. A patterned mask layer is formed on the semiconductor substrate, and the semiconductor substrate is etched using the patterned mask layer as an etching mask to form a plurality of second trenches. The patterned mask layer is removed. Each second trench is filled with an insulating layer acting as an isolation. Each of first conducting layers is etched to form a plurality of grooves. A doped area acting as a buried strap is formed in the semiconductor substrate beside each groove. A trench top insulating layer is formed in the bottom surface of each trench. Each first trench is filled with a second conducting layer acting as a gate.
摘要翻译：一种用于在垂直DRAM中形成隔离层的方法。提供了具有多个第一沟槽的半导体衬底，其中，在每个的侧壁上形成一个环形电介质层，并且各自填充有第一导电层。在半导体衬底上形成图案化掩模层，并使用图案化掩模层作为蚀刻掩模蚀刻半导体衬底，以形成多个第二沟槽。去除图案化的掩模层。每个第二沟槽填充有用作隔离层的绝缘层。每个第一导电层被蚀刻以形成多个凹槽。在每个沟槽旁边的半导体衬底中形成用作掩埋带的掺杂区域。沟槽顶部绝缘层形成在每个沟槽的底表面中。每个第一沟槽填充有用作栅极的第二导电层。

9. 发明授权

US06800895B2 Vertical split gate flash memory cell and method for fabricating the same 有权
标题翻译：垂直分裂门闪存单元及其制造方法
公开(公告)号：US06800895B2
公开(公告)日：2004-10-05
申请号：US10272176
申请日：2002-10-15
申请人： Ming Cheng Chang , Cheng-Chih Huang , Jeng-Ping Lin
发明人： Ming Cheng Chang , Cheng-Chih Huang , Jeng-Ping Lin
IPC分类号： H01L29788
CPC分类号： H01L27/11556 , H01L27/115 , H01L29/42336 , H01L29/7881
摘要： A vertical split gate flash memory cell. The memory cell includes a substrate, a floating gate, a control gate, a tunnel layer, a first doping region, and a second doping region. The floating gate is disposed in the lower portion of the trench and insulated from the adjacent substrate by a floating gate oxide layer. The control gate is disposed over the floating gate and insulated from the adjacent substrate by a control gate oxide layer. The inter-gate dielectric layer is disposed between the floating gate and the control gate for insulation of the floating gate and the control gate. The first doping region is formed in the substrate adjacent to the control gate and the second doping region is formed in the substrate below the first doping region and adjacent to the floating gate to serve as source and drain regions with the first doping region.
摘要翻译：垂直分闸门闪存单元。存储单元包括衬底，浮置栅极，控制栅极，隧道层，第一掺杂区域和第二掺杂区域。浮动栅极设置在沟槽的下部，并通过浮栅氧化层与相邻衬底绝缘。控制栅极设置在浮置栅极上并通过控制栅极氧化物层与相邻衬底绝缘。栅极间电介质层设置在浮置栅极和控制栅极之间，用于浮动栅极和控制栅极的绝缘。第一掺杂区域形成在与控制栅极相邻的衬底中，并且第二掺杂区域形成在第一掺杂区域下方的衬底中并且与浮置栅极相邻，以用作具有第一掺杂区域的源极和漏极区域。

10. 发明授权

US06800526B2 Method for manufacturing a self-aligned split-gate flash memory cell 有权
标题翻译：用于制造自对准分裂闸闪存单元的方法
公开(公告)号：US06800526B2
公开(公告)日：2004-10-05
申请号：US10302865
申请日：2002-11-25
申请人： Chi-Hui Lin , Chung-Lin Huang , Cheng-Chih Huang
发明人： Chi-Hui Lin , Chung-Lin Huang , Cheng-Chih Huang
IPC分类号： H01L21336
CPC分类号： H01L29/42332 , H01L21/28273
摘要： A method for manufacturing a split-gate flash memory cell, comprising the steps of forming an active region on a semiconductor substrate; forming a buffer layer on the semiconductor substrate; forming a first dielectric layer on the buffer layer; removing part of the first dielectric layer; defining an opening; removing the buffer layer within the opening; forming a gate insulating layer and floating gates; forming a source region in the semiconductor substrate; depositing a conformal second dielectric layer on the opening; removing the buffer layer outside the first dielectric layer and the floating gates; and forming an oxide layer and control gates.
摘要翻译：一种分离栅闪存单元的制造方法，包括以下步骤：在半导体衬底上形成有源区; 在半导体衬底上形成缓冲层; 在缓冲层上形成第一介电层; 去除所述第一电介质层的一部分; 定义一个开口去除开口内的缓冲层; 形成栅绝缘层和浮栅; 在所述半导体衬底中形成源区; 在开口上沉积共形的第二介电层; 去除第一介电层和浮栅之外的缓冲层; 并形成氧化物层和控制栅极。

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