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1. 发明授权

US09225499B2 Method, apparatus and system of transferring data between elements of a cable communication device 有权
标题翻译：在有线通信设备的元件之间传送数据的方法，装置和系统
公开(公告)号：US09225499B2
公开(公告)日：2015-12-29
申请号：US13976468
申请日：2012-03-28
申请人： Shaul Shulman , Dmitrii A. Loukianov , Naor Goldman , Bernard Arambepola
发明人： Shaul Shulman , Dmitrii A. Loukianov , Naor Goldman , Bernard Arambepola
IPC分类号： H04L5/14 , H04L1/00
CPC分类号： H04L5/14 , H04L1/0041 , H04L1/0083 , H04L12/2801 , H04L27/0002 , H04M11/00 , H04N21/6118 , H04N21/6168
摘要： Some demonstrative embodiments include devices, systems and methods of transferring information between elements of a communication device. For example, a device may include a front-end to receive an analog downstream input including a plurality of downstream data channels, and to provide a digital serial downstream output including at least one continuous stream of constant-size downstream frames including a plurality of constant-size downstream data frames, which include downstream sample data of the plurality of downstream data channels; a serial interface including at least one serial lane to transfer the at least on stream of the digital serial downstream output; and a processor to receive the digital serial downstream over the serial interface, and to process the downstream data frames.
摘要翻译：一些演示实施例包括在通信设备的元件之间传送信息的设备，系统和方法。例如，设备可以包括前端以接收包括多个下游数据信道的模拟下游输入，并且提供数字串行下游输出，其包括至少一个恒定尺寸的下游帧的连续流，包括多个常数确定下游数据帧，其包括所述多个下游数据信道的下游采样数据; 串行接口，包括至少一个串行通道，用于传输数字串行下游输出的至少上游; 以及处理器，通过串行接口接收数字串行下游，并处理下游数据帧。

2. 发明申请

US20130272357A1 METHOD, APPARATUS AND SYSTEM OF TRANSFERRING DATA BETWEEN ELEMENTS OF A CABLE COMMUNICATION DEVICE 有权
标题翻译：方法，传输电缆通信设备元件数据的装置和系统
公开(公告)号：US20130272357A1
公开(公告)日：2013-10-17
申请号：US13976468
申请日：2012-03-28
申请人： Shaul Shulman , Dmitrii A. Loukianov , Naor Goldman , Bernard Arambepola
发明人： Shaul Shulman , Dmitrii A. Loukianov , Naor Goldman , Bernard Arambepola
IPC分类号： H04L5/14
CPC分类号： H04L5/14 , H04L1/0041 , H04L1/0083 , H04L12/2801 , H04L27/0002 , H04M11/00 , H04N21/6118 , H04N21/6168
摘要： Some demonstrative embodiments include devices, systems and methods of transferring information between elements of a communication device. For example, a device may include a front-end to receive an analog downstream input including a plurality of downstream data channels, and to provide a digital serial downstream output including at least one continuous stream of constant-size downstream frames including a plurality of constant-size downstream data frames, which include downstream sample data of the plurality of downstream data channels; a serial interface including at least one serial lane to transfer the at least on stream of the digital serial downstream output; and a processor to receive the digital serial downstream over the serial interface, and to process the downstream data frames.
摘要翻译：一些演示实施例包括在通信设备的元件之间传送信息的设备，系统和方法。例如，设备可以包括前端以接收包括多个下游数据信道的模拟下游输入，并且提供数字串行下游输出，其包括至少一个恒定尺寸的下游帧的连续流，包括多个常数确定下游数据帧，其包括所述多个下游数据信道的下游采样数据; 串行接口，包括至少一个串行通道，用于传输数字串行下游输出的至少上游; 以及处理器，通过串行接口接收数字串行下游，并处理下游数据帧。

3. 发明授权

US08781052B2 Physical layer channel synchronization method for high bit-rate cable transmissions 失效
标题翻译：用于高比特率电缆传输的物理层信道同步方法
公开(公告)号：US08781052B2
公开(公告)日：2014-07-15
申请号：US13529366
申请日：2012-06-21
申请人： Bernard Arambepola , Shaul Shulman , Naor Goldman , Amos Klimker , Noam Tal
发明人： Bernard Arambepola , Shaul Shulman , Naor Goldman , Amos Klimker , Noam Tal
IPC分类号： H04J3/06 , H04L7/04 , H04L7/00
CPC分类号： H04N21/6118 , H04L25/14 , H04L27/34 , H04N21/4382 , H04N21/4385 , H04N21/4622 , H04N21/631
摘要： A system and method are described to provide a next generation cable gateway/modem based on the DOCSIS standard with a scheme to synchronously combine channels in the physical layer to increase overall bit rates for coaxial cable data transmission. The systems and methods synchronize the counters associated with multiple channels, including continuity counters, at the transmitter to zero and then allow the counters on individual channels to increment individually. At the receiver, individual channel delays of individual channels will be thus recognizable based on the information provided by the counters associated with each channel. A buffer at the receiver is informed and used to individually delay one or more of the multiple channels to marry up continuity counter values. In this manner, the buffer acts to essentially equalize delays in individual channels with the continuity counter representing the mechanism for specifying the individual delays for the separate channels.
摘要翻译：描述了一种系统和方法来提供基于DOCSIS标准的下一代电缆网关/调制解调器，其具有同步组合物理层中的信道以增加用于同轴电缆数据传输的总比特率的方案。系统和方法将发射机处的与多个通道相关联的计数器（包括连续性计数器）同步到零，然后允许各个通道上的计数器单独增加。在接收机处，基于与每个信道相关联的计数器提供的信息，各个信道的各个信道延迟将因此被识别。接收器处的缓冲器被通知并用于单独延迟多个通道中的一个或多个以结束连续性计数器值。以这种方式，缓冲器用于基本上均衡各个信道中的延迟，连续性计数器表示用于指定单独信道的各个延迟的机制。

4. 发明申请

US20130343501A1 PHYSICAL LAYER CHANNEL SYNCHRONIZATION METHOD FOR HIGH BIT-RATE CABLE TRANSMISSIONS 失效
标题翻译：高速电缆传输的物理层通道同步方法
公开(公告)号：US20130343501A1
公开(公告)日：2013-12-26
申请号：US13529366
申请日：2012-06-21
申请人： Bernard Arambepola , Shaul Shulman , Naor Goldman , Amos Klimker , Noam Tal
发明人： Bernard Arambepola , Shaul Shulman , Naor Goldman , Amos Klimker , Noam Tal
IPC分类号： H04L7/00
CPC分类号： H04N21/6118 , H04L25/14 , H04L27/34 , H04N21/4382 , H04N21/4385 , H04N21/4622 , H04N21/631
摘要： A system and method are described to provide a next generation cable gateway/modem based on the DOCSIS standard with a scheme to synchronously combine channels in the physical layer to increase overall bit rates for coaxial cable data transmission. The systems and methods synchronize the counters associated with multiple channels, including continuity counters, at the transmitter to zero and then allow the counters on individual channels to increment individually. At the receiver, individual channel delays of individual channels will be thus recognizable based on the information provided by the counters associated with each channel. A buffer at the receiver is informed and used to individually delay one or more of the multiple channels to many up continuity counter values. In this manner, the buffer acts to essentially equalize delays in individual channels with the continuity counter representing the mechanism for specifying the individual delays for the separate channels.
摘要翻译：描述了一种系统和方法来提供基于DOCSIS标准的下一代电缆网关/调制解调器，其具有同步组合物理层中的信道以增加用于同轴电缆数据传输的总比特率的方案。系统和方法将发射机处的与多个通道相关联的计数器（包括连续性计数器）同步到零，然后允许各个通道上的计数器单独增加。在接收机处，基于与每个信道相关联的计数器提供的信息，各个信道的各个信道延迟将因此被识别。接收器处的缓冲器被通知并用于将多个通道中的一个或多个单独地延迟到许多向上的连续性计数器值。以这种方式，缓冲器用于基本上均衡各个信道中的延迟，连续性计数器表示用于指定单独信道的各个延迟的机制。

5. 发明申请

US20140247782A1 Configurable Constellation Mapping to Control Spectral Efficiency Versus Signal-to-Noise Ratio 有权
标题翻译：可配置星座映射控制光谱效率与信噪比
公开(公告)号：US20140247782A1
公开(公告)日：2014-09-04
申请号：US14197208
申请日：2014-03-04
申请人： Bernard Arambepola , Noam Tal , Sahan S. Gamage , Thushara Hewavithana , Shaul Shulman
发明人： Bernard Arambepola , Noam Tal , Sahan S. Gamage , Thushara Hewavithana , Shaul Shulman
IPC分类号： H04L5/00 , H04L1/00
CPC分类号： H04L1/004 , H04L1/0041 , H04L5/0046 , H04L27/0008 , H04L27/2634
摘要： Mixed mode constellation mapping to map a data block to a block of sub-carriers based on a configurable set of one or more constellation mapping schemes, and corresponding mixed mode least likelihood ratio (LLR) de-mapping based on the configurable set of one or more modulation schemes. The set may be configurable to include multiple modulation schemes to provide to a SEvSNR measure that is a non-weighted or weighted average of SEvSNR measures of the multiple modulation schemes. Mixed mode constellation mapping may be useful be configurable to control spectral efficiency versus SNR (SEvSNR) over a range of SNR with relatively fine SNR granularity, and may be configurable to control SEvSNR over a range of SNR at a fixed FEC code rate, which may include a highest available or highest permitted code rate.
摘要翻译：基于可配置的一个或多个星座映射方案集合以及相应的混合模式最小似然比（LLR）去映射的混合模式星座图映射，以将数据块映射到子载波块，基于可配置的一个或多个更多的调制方案。该集合可以被配置为包括多个调制方案以提供SEvSNR度量，其是多个调制方案的SEvSNR度量的非加权或加权平均。混合模式星座映射可能是有用的，可以被配置为在具有相对精细的SNR粒度的SNR范围内控制频谱效率与SNR（SEvSNR），并且可以被配置为以固定的FEC码率在SNR范围内控制SEvSNR，包括最高可用或最高允许码率。

6. 发明申请

US20140185657A1 SYSTEMS AND METHODS FOR IMPLEMENTING SOFT-DECISION REED-SOLOMON DECODING TO IMPROVE CABLE MODEM AND CABLE GATEWAY PERFORMANCE 有权
标题翻译：实施软决策解决方案改进电缆调制解调器和电缆网关性能的系统和方法
公开(公告)号：US20140185657A1
公开(公告)日：2014-07-03
申请号：US13728022
申请日：2012-12-27
申请人： Bernard Arambepola , Murat Badem , Parveen K. Shukla , Sahan Gamage , Thushara Hewavithana , Naor Goldman
发明人： Bernard Arambepola , Murat Badem , Parveen K. Shukla , Sahan Gamage , Thushara Hewavithana , Naor Goldman
IPC分类号： H04L27/06
CPC分类号： H04L27/06 , H03M13/1515 , H03M13/451 , H03M13/453 , H04L1/0045 , H04L1/0047 , H04L1/0057 , H04L27/38
摘要： A system and method are provided for implementing a soft Reed-Solomon (RS) decoding scheme, technique or algorithm to improve physical layer performance in cable modems and cable gateways. At 1024-QAM, a receiver is provided in which a signal to noise ratio is reduced by at least about 1 dB relaxing design considerations and specifications for other components in the system including for the tuner. A soft-RS-symbol generation scheme is provided to enable soft-input RC decoding in a forward error correction (FEC) module connected to a QAM demodulator. The RS decoding scheme is implemented without significantly complicating hardware or processing overhead. A typical receiver hardware requirement in an FEC module to implement the disclosed scheme may be comparatively modest, e.g., on an order of approximately 50K gates.
摘要翻译：提供了一种用于实现软的里德 - 所罗门（RS）解码方案，技术或算法以改善电缆调制解调器和电缆网关中的物理层性能的系统和方法。在1024-QAM中，提供了一种接收机，其中信噪比降低了包括用于调谐器的系统中其他部件的至少约1dB的松弛设计考虑和规格。提供软RS符号生成方案以在连接到QAM解调器的前向纠错（FEC）模块中实现软输入RC解码。实现RS解码方案，而不会使硬件或处理开销显着复杂化。用于实现所公开的方案的FEC模块中的典型接收机硬件要求可以是相对适中的，例如大约50K门的量级。

7. 发明授权

US09106497B2 Apparatus and method for improving OFDM receiver performance in the presence of narrowband interferers 有权
标题翻译：在存在窄带干扰的情况下改善OFDM接收机性能的装置和方法
公开(公告)号：US09106497B2
公开(公告)日：2015-08-11
申请号：US13596993
申请日：2012-08-28
申请人： Bernard Arambepola , Thushara Hewavithana
发明人： Bernard Arambepola , Thushara Hewavithana
IPC分类号： H04L25/08 , H04L1/00 , H04B1/10 , H04L27/26 , H03K6/04 , H03K5/01 , H03D1/06 , H03D1/04
CPC分类号： H04L27/265 , H04L27/2657 , H04L27/2688 , H04L27/2691
摘要： In an Orthogonal Frequency Division Multiplex (“OFDM”) system, the problem of an interferer reducing the signal-to-noise ratio of a signal can be mitigated by generating an interferer-correction signal and subtracting it from the signal to be processed. The amplitude, frequency and phase of the interferences are determined first. The frequency is estimated by averaging the squared-magnitude of multiple FFTs of the incoming signal and then locating the spectral peaks. The phase and amplitude may be estimated from this FFT outputs or through a process of correlation in the time domain. The interferer-correction signal is generated from the estimated amplitude, frequency, and phase. The correction to be subtracted from the main signal in order to reduce the effect of the interference may be generated in the time or frequency domain. The subtraction of the correction may also be implemented in the time or frequency domains.
摘要翻译：在正交频分复用（“OFDM”）系统中，可以通过产生干扰校正信号并从要处理的信号中减去干扰源来减少信号的信噪比的问题。首先确定干扰的幅度，频率和相位。通过对输入信号的多个FFT的平方幅度进行平均，然后定位频谱峰值来估计频率。可以从该FFT输出或通过时域中的相关过程来估计相位和幅度。从估计的幅度，频率和相位产生干扰校正信号。可以在时域或频域中产生要从主信号中减去以减少干扰的影响的校正。校正的减法也可以在时域或频域中实现。

8. 发明授权

US08938015B2 Orthogonal frequency division multiplex (OFDM) demodulator with improved cyclic ambiguity resolution 有权
标题翻译：具有改进的循环模糊度分辨率的正交频分复用（OFDM）解调器
公开(公告)号：US08938015B2
公开(公告)日：2015-01-20
申请号：US13997706
申请日：2012-03-15
申请人： Bernard Arambepola , Thushara Hewavithana
发明人： Bernard Arambepola , Thushara Hewavithana
IPC分类号： H04L27/22 , H04L27/01 , H04B17/00 , H04L27/26
CPC分类号： H04L27/22 , H04L25/03159 , H04L27/01 , H04L27/26 , H04L27/2665 , H04L27/2672 , H04L27/2675 , H04L27/2679 , H04L27/2695
摘要： A system according to one embodiment includes a demodulator configured to receive an OFDM modulated signal over a channel, the signal including a sequence of symbols, each of the symbols including one or more pilot carriers and one or more data carriers; a time filtering and interpolation circuit coupled to the demodulator, the time filtering and interpolation circuit configured to estimate the frequency response of the channel based on time filtering and interpolation of the pilot carriers; a phase slope correction circuit configured to apply each of a plurality of phase slope corrections to the frequency response and to the data carriers; a frequency filtering and interpolation circuit configured to calculate frequency response estimates of the channel at data carrier frequencies based on frequency filtering and interpolation of the phase slope corrected frequency response; an equalization circuit configured to equalize the phase slope corrected data carriers based on the calculated frequency response estimates; an error calculation circuit configure to calculate the mean square error between the equalized data carriers and a nearest QAM constellation point; and an iterative phase slope optimization circuit configured to select the phase slope correction associated with the minimum of the mean square errors, wherein the selected phase slope resolves the cyclic ambiguity.
摘要翻译：根据一个实施例的系统包括：解调器，被配置为通过信道接收OFDM调制信号，所述信号包括符号序列，每个符号包括一个或多个导频载波和一个或多个数据载波; 耦合到解调器的时间滤波和内插电路，所述时间滤波和内插电路被配置为基于导频载波的时间滤波和内插来估计信道的频率响应; 相位斜率校正电路，被配置为对频率响应和数据载波施加多个相位斜率校正中的每一个; 频率滤波和内插电路，被配置为基于频率滤波和相位斜率校正频率响应的内插来计算数据载波频率处的信道的频率响应估计; 均衡电路，被配置为基于所计算的频率响应估计来均衡相位斜率校正数据载波; 误差计算电路，用于计算均衡数据载波与最近的QAM星座点之间的均方误差; 以及迭代相位斜率优化电路，被配置为选择与所述均方误差的最小值相关联的相位斜率校正，其中所选择的相位斜率解决所述循环模糊度。

9. 发明授权

US08897412B2 Method and apparatus for phase noise mitigation 有权
标题翻译：减噪相位噪声的方法和装置
公开(公告)号：US08897412B2
公开(公告)日：2014-11-25
申请号：US13714530
申请日：2012-12-14
申请人： Thushara Hewavithana , Bernard Arambepola
发明人： Thushara Hewavithana , Bernard Arambepola
IPC分类号： H04B1/10 , H04L27/01 , H04L27/26
CPC分类号： H04L27/01 , H04L27/2647 , H04L27/3836 , H04L2027/0038 , H04L2027/0087
摘要： An approach is provided to mitigate phase noise by correcting common phase error and inter-carrier-interference in a received signal. The approach involves determining a received signal includes phase noise comprising at least a common phase error component and an inter-carrier-interference component. The approach also involves causing the common phase error to be corrected based on one or more pilot carriers. The approach further involves causing an estimate of a main signal component to be subtracted from the one or more pilot carriers. The approach additionally involves determining a sequence of estimated coefficients of a multiplicative phase noise sequence. The approach also involves causing the inter-carrier-inference to be corrected by processing the multiplicative phase noise sequence using the sequence of estimated coefficients. The approach further involves causing an equalized data signal to be output based on the corrected common phase error and the corrected inter-carrier-interference.
摘要翻译：提供了一种通过校正接收信号中的公共相位误差和载波间干扰来减轻相位噪声的方法。该方法包括确定接收信号包括至少包括公共相位误差分量和载波间干扰分量的相位噪声。该方法还涉及基于一个或多个导频载波来校正公共相位误差。该方法还包括导致从一个或多个导频载波减去主信号分量的估计。该方法还涉及确定乘法相位噪声序列的估计系数序列。该方法还涉及通过使用估计系数的序列处理乘法相位噪声序列来使得载波间推理被校正。该方法进一步包括使得基于校正的公共相位误差和校正的载波间干扰来输出均衡的数据信号。

10. 发明授权

US08606209B2 Apparatus and methods for efficient implementation of tuners 失效
标题翻译：调谐器有效实现的装置和方法
公开(公告)号：US08606209B2
公开(公告)日：2013-12-10
申请号：US12459006
申请日：2009-06-24
申请人： Nicholas Cowley , Isaac Ali , Bernard Arambepola
发明人： Nicholas Cowley , Isaac Ali , Bernard Arambepola
IPC分类号： H04B1/26
CPC分类号： H03J1/0083 , H03J1/005
摘要： Embodiments of systems and methods for the efficient implementation of tuners are generally described herein. Other embodiments may be described and claimed.
摘要翻译：有效实施调谐器的系统和方法的实施例一般在此描述。可以描述和要求保护其他实施例。

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