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1. 发明申请

US20090004818A1 Method of Fabricating Flash Memory Device 审中-公开
标题翻译：制造闪存设备的方法
公开(公告)号：US20090004818A1
公开(公告)日：2009-01-01
申请号：US11956865
申请日：2007-12-14
申请人： Seung Woo Shin , Eun Soo Kim , Suk Joong Kim , Jong Hye Cho
发明人： Seung Woo Shin , Eun Soo Kim , Suk Joong Kim , Jong Hye Cho
IPC分类号： H01L21/762
CPC分类号： H01L21/76232 , H01L27/11521
摘要： Disclosed herein is a method of fabricating a semiconductor flash memory device, which method avoids and prevents damage to the conductive layer of a floating gate. The disclosed method can prevent a reduction in the charge trap density characteristics and improve the yield of the device.
摘要翻译：本文公开了一种制造半导体闪速存储器件的方法，该方法避免并防止对浮动栅极的导电层的损坏。所公开的方法可以防止电荷陷阱密度特性的降低并且提高器件的产量。

2. 发明申请

US20090029522A1 Method of Forming Isolation Layer of Semiconductor Device 审中-公开
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US20090029522A1
公开(公告)日：2009-01-29
申请号：US11954470
申请日：2007-12-12
申请人： Whee Won Cho , Seung Hee Hong , Suk Joong Kim , Jong Hye Cho
发明人： Whee Won Cho , Seung Hee Hong , Suk Joong Kim , Jong Hye Cho
IPC分类号： H01L21/762
CPC分类号： H01L21/76232 , H01L21/31116
摘要： A method of forming isolation layers of a semiconductor device including forming a first insulating layer on a semiconductor substrate including trenches formed in the semiconductor substrate, substituting a top surface of the first insulating layer with salt, removing the salt to expand a space between sidewalls of the first insulating layer, and forming a second insulating layer on the first insulating layer so that the trenches are gap-filled. Thus, trenches can be easily gap-filled with an insulating material.
摘要翻译：一种形成半导体器件的隔离层的方法，包括在半导体衬底上形成第一绝缘层，该半导体衬底包括在半导体衬底中形成的沟槽，用盐代替第一绝缘层的顶表面，除去盐以扩大第二绝缘层的侧壁之间的空间第一绝缘层，并且在第一绝缘层上形成第二绝缘层，使得沟槽间隙填充。因此，沟槽可以容易地用绝缘材料间隙填充。

3. 发明申请

US20080268612A1 METHOD OF FORMING ISOLATION LAYER IN SEMICONDUCTOR DEVICE 审中-公开
标题翻译：在半导体器件中形成隔离层的方法
公开(公告)号：US20080268612A1
公开(公告)日：2008-10-30
申请号：US11962611
申请日：2007-12-21
申请人： Whee Won Cho , Cheol Mo Jeong , Jung Geun Kim , Suk Joong Kim , Jong Hye Cho
发明人： Whee Won Cho , Cheol Mo Jeong , Jung Geun Kim , Suk Joong Kim , Jong Hye Cho
IPC分类号： H01L21/762
CPC分类号： H01L21/76232
摘要： The present invention discloses to a method of forming an isolation layer in a semiconductor device. In particular, the method of forming an isolation layer in a semiconductor device of the present invention comprises the steps of providing a semiconductor substrate on which a trench is formed; forming spacers on side walls of the trench; forming a first insulating layer to fill a portion of the trench such that a deposition rate on the semiconductor substrate which is a bottom surface of the trench and exposed between the spacers is higher than that on a surface of the space; and forming a second insulating layer on the first insulating layer so as to fill the trench with the second insulating layer. An O3-TEOS layer on the exposed semiconductor substrate which is a bottom surface of the trench is grown faster than that on a surface of the spacer formed of an oxide layer or a nitride layer to prevent the O3-TEOS layers grown on the side walls from coming into contact with each other, and so it is possible to inhibit a generation of a seam and to enhance a gap-filling characteristic for the trench.
摘要翻译：本发明公开了一种在半导体器件中形成隔离层的方法。特别地，本发明的半导体器件中形成隔离层的方法包括以下步骤：提供其上形成有沟槽的半导体衬底; 在沟槽的侧壁上形成间隔物; 形成第一绝缘层以填充所述沟槽的一部分，使得作为所述沟槽的底表面并暴露在所述间隔物之间的所述半导体衬底上的沉积速率高于所述空间的表面上的沉积速率; 以及在所述第一绝缘层上形成第二绝缘层以便用所述第二绝缘层填充所述沟槽。作为沟槽底面的暴露的半导体衬底上的O 3 -TOS层比由氧化物层或氮化物层形成的间隔物的表面上生长得快，以防止O 在侧壁上生长的3层以上的层彼此接触，因此可以抑制接缝的产生并且增强沟槽的间隙填充特性。

4. 发明申请

US20080160753A1 Method of forming metal wire in semiconductor device 有权
标题翻译：在半导体器件中形成金属线的方法
公开(公告)号：US20080160753A1
公开(公告)日：2008-07-03
申请号：US11801498
申请日：2007-05-10
申请人： Eun Soo Kim , Jung Geun Kim , Suk Joong Kim
发明人： Eun Soo Kim , Jung Geun Kim , Suk Joong Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76882 , H01L23/53223 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal wire in a semiconductor device is disclosed The method includes the steps of etching an insulating layer formed on a semiconductor substrate to form a dual damascene pattern, forming a barrier metal layer in the dual damascene pattern, forming a metal layer on the barrier metal layer, and filling the dual damascene pattern with a conductive material to form a metal wire.
摘要翻译：公开了一种在半导体器件中形成金属线的方法。该方法包括以下步骤：蚀刻在半导体衬底上形成的绝缘层，以形成双镶嵌图案，在双镶嵌图案中形成阻挡金属层，形成金属层在阻挡金属层上，并用导电材料填充双镶嵌图案以形成金属线。

5. 发明申请

US20090004817A1 METHOD OF FORMING ISOLATION LAYER OF SEMICONDUCTOR DEVICE 失效
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US20090004817A1
公开(公告)日：2009-01-01
申请号：US11955881
申请日：2007-12-13
申请人： Jung Geun Kim , Eun Soo Kim , Seung Hee Hong , Suk Joong Kim
发明人： Jung Geun Kim , Eun Soo Kim , Seung Hee Hong , Suk Joong Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： A method of forming an isolation layer of a semiconductor device is disclosed herein, the method comprising the steps of providing a semiconductor substrate in which a tunnel insulating layer and a charge storage layer are formed on an active area and a trench is formed on an isolation area; forming a first insulating layer for filling a lower portion of the trench; forming a porous second insulating layer on the first insulating layer for filling a space between the charge storage layers; forming a third insulating layer on a side wall of the trench and the second insulating layer, the third insulating layer having a density higher than that of the second insulating layer; and forming a porous fourth insulating layer for filling the trench.
摘要翻译：本文公开了形成半导体器件的隔离层的方法，该方法包括以下步骤：提供在有源区上形成隧道绝缘层和电荷存储层的半导体衬底，并且在隔离层上形成沟槽区; 形成用于填充沟槽的下部的第一绝缘层; 在所述第一绝缘层上形成多孔第二绝缘层，用于填充所述电荷存储层之间的空间; 在所述沟槽和所述第二绝缘层的侧壁上形成第三绝缘层，所述第三绝缘层的密度高于所述第二绝缘层的密度; 以及形成用于填充所述沟槽的多孔第四绝缘层。

6. 发明申请

US20080105983A1 Method of forming metal line of semiconductor device, and semiconductor device 失效
标题翻译：半导体器件金属线形成方法及半导体器件
公开(公告)号：US20080105983A1
公开(公告)日：2008-05-08
申请号：US11604484
申请日：2006-11-27
申请人： Cheol Mo Jeong , Seong Hwan Myung , Eun Soo Kim , Suk Joong Kim
发明人： Cheol Mo Jeong , Seong Hwan Myung , Eun Soo Kim , Suk Joong Kim
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L23/53266 , H01L21/28562 , H01L21/76843 , H01L21/76846 , H01L21/76856 , H01L21/76876 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first barrier metal layer and a second barrier metal layer, a third barrier metal layer, and a metal line. The first barrier metal layer and the second barrier metal layer are formed and on a top surface of an insulating layer over a semiconductor substrate on the bottom surface of trenches formed in the insulating layer. The third barrier metal layer is formed on sidewalls of trenches. The metal line gap-fills the trenches. In a method of forming a metal line of a semiconductor device, trenches are formed within an insulating layer over a semiconductor substrate. A first barrier metal layer and a second barrier metal layer are formed on a bottom surface of the trenches and on a top surface of the insulating layer. A third barrier metal layer is formed on sidewalls of trenches. A metal line gap-fills the trenches.
摘要翻译：半导体器件包括第一阻挡金属层和第二阻挡金属层，第三阻挡金属层和金属线。第一阻挡金属层和第二阻挡金属层形成在半导体衬底上的形成在绝缘层的沟槽的底表面上的绝缘层的顶表面上。第三阻挡金属层形成在沟槽的侧壁上。金属线间隙填充沟槽。在形成半导体器件的金属线的方法中，在半导体衬底上的绝缘层内形成沟槽。第一阻挡金属层和第二阻挡金属层形成在沟槽的底表面和绝缘层的顶表面上。第三阻挡金属层形成在沟槽的侧壁上。金属线间隙填充沟槽。

7. 发明申请

US20090023279A1 METHOD OF FABRICATING FLASH MEMORY DEVICE 失效
标题翻译：制造闪存存储器件的方法
公开(公告)号：US20090023279A1
公开(公告)日：2009-01-22
申请号：US12131626
申请日：2008-06-02
申请人： Eun Soo Kim , Jung Geun Kim , Suk Joong Kim
发明人： Eun Soo Kim , Jung Geun Kim , Suk Joong Kim
IPC分类号： H01L21/311 , H01L21/28
CPC分类号： H01L21/764 , H01L27/115 , H01L27/11521
摘要： The present invention relates to a method of fabricating a flash memory device and includes forming an air-gap having a low dielectric constant between word lines and floating gates. Further, a tungsten nitride (WN) layer is formed on sidewalls of a tungsten (W) layer for a control gate. Hence, the cross section of the control gate that is finally formed can be increased while preventing abnormal oxidization of the tungsten layer in a subsequent annealing process. The method of the present invention can improve interference between neighboring word lines and, thus improve the reliability of a device. Accordingly, a robust high-speed device can be implemented.
摘要翻译：本发明涉及一种制造闪速存储器件的方法，包括在字线和浮栅之间形成具有低介电常数的气隙。此外，在用于控制栅极的钨（W）层的侧壁上形成氮化钨（WN）层。因此，可以提高最终形成的控制栅极的横截面，同时防止随后的退火工艺中钨层的异常氧化。本发明的方法可以改善相邻字线之间的干扰，从而提高设备的可靠性。因此，可以实现鲁棒的高速设备。

8. 发明申请

US20090004819A1 Method of Fabricating Flash Memory Device 审中-公开
标题翻译：制造闪存设备的方法
公开(公告)号：US20090004819A1
公开(公告)日：2009-01-01
申请号：US11963906
申请日：2007-12-24
申请人： Whee Won Cho , Eun Soo Kim , Suk Joong Kim
发明人： Whee Won Cho , Eun Soo Kim , Suk Joong Kim
IPC分类号： H01L21/76
CPC分类号： H01L27/115 , H01L27/11521
摘要： In one aspect of the inventive method, a tunnel insulating film, a first conductive layer, and an isolation mask pattern are formed over a semiconductor substrate. The first conductive layer and the tunnel insulating film are patterned along the isolation mask pattern. A trench is formed in the semiconductor substrate. The trench is gap filled with a first insulating film. A polishing process is performed in order to expose the first conductive layer. A height of the first insulating film is lowered. The first conductive layer on the first insulating film is gap-filled with a second insulating film.
摘要翻译：在本发明方法的一个方面中，在半导体衬底上形成隧道绝缘膜，第一导电层和隔离掩模图案。第一导电层和隧道绝缘膜沿着隔离掩模图案被图案化。在半导体衬底中形成沟槽。沟槽填充有第一绝缘膜。进行抛光处理以露出第一导电层。第一绝缘膜的高度降低。第一绝缘膜上的第一导电层用第二绝缘膜间隙填充。

9. 发明授权

US08163627B2 Method of forming isolation layer of semiconductor device 失效
标题翻译：形成半导体器件隔离层的方法
公开(公告)号：US08163627B2
公开(公告)日：2012-04-24
申请号：US11955881
申请日：2007-12-13
申请人： Jung Geun Kim , Eun Soo Kim , Seung Hee Hong , Suk Joong Kim
发明人： Jung Geun Kim , Eun Soo Kim , Seung Hee Hong , Suk Joong Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： A method of forming an isolation layer of a semiconductor device is disclosed herein, the method comprising the steps of providing a semiconductor substrate in which a tunnel insulating layer and a charge storage layer are formed on an active area and a trench is formed on an isolation area; forming a first insulating layer for filling a lower portion of the trench; forming a porous second insulating layer on the first insulating layer for filling a space between the charge storage layers; forming a third insulating layer on a side wall of the trench and the second insulating layer, the third insulating layer having a density higher than that of the second insulating layer; and forming a porous fourth insulating layer for filling the trench.
摘要翻译：本文公开了形成半导体器件的隔离层的方法，该方法包括以下步骤：提供在有源区上形成隧道绝缘层和电荷存储层的半导体衬底，并且在隔离层上形成沟槽区; 形成用于填充沟槽的下部的第一绝缘层; 在所述第一绝缘层上形成多孔第二绝缘层，用于填充所述电荷存储层之间的空间; 在所述沟槽和所述第二绝缘层的侧壁上形成第三绝缘层，所述第三绝缘层的密度高于所述第二绝缘层的密度; 以及形成用于填充所述沟槽的多孔第四绝缘层。

10. 发明授权

US07682967B2 Method of forming metal wire in semiconductor device 有权
标题翻译：在半导体器件中形成金属线的方法
公开(公告)号：US07682967B2
公开(公告)日：2010-03-23
申请号：US11801498
申请日：2007-05-10
申请人： Eun Soo Kim , Jung Geun Kim , Suk Joong Kim
发明人： Eun Soo Kim , Jung Geun Kim , Suk Joong Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76882 , H01L23/53223 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal wire in a semiconductor device is disclosed The method includes the steps of etching an insulating layer formed on a semiconductor substrate to form a dual damascene pattern, forming a barrier metal layer in the dual damascene pattern, forming a metal layer on the barrier metal layer, and filling the dual damascene pattern with a conductive material to form a metal wire.
摘要翻译：公开了一种在半导体器件中形成金属线的方法。该方法包括以下步骤：蚀刻在半导体衬底上形成的绝缘层，以形成双镶嵌图案，在双镶嵌图案中形成阻挡金属层，形成金属层在阻挡金属层上，并用导电材料填充双镶嵌图案以形成金属线。

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