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    • 4. 发明申请
    • HIGH VOLTAGE ESD POWER CLAMP
    • 高电压ESD功率钳位
    • US20060072267A1
    • 2006-04-06
    • US10711748
    • 2004-10-01
    • Kiran ChattyRobert GauthierMahmoud MousaMujahid MuhammadChristopher Putnam
    • Kiran ChattyRobert GauthierMahmoud MousaMujahid MuhammadChristopher Putnam
    • H03K19/0175
    • H01L27/0266H03K17/08142
    • A structure and apparatus is provided for an electrostatic discharge power clamp, for use with high voltage power supplies. The power clamp includes a network of transistor devices, for example, nFETs arranged in series between a power rail and a ground rail. The first transistor device is biased into a partially on-state, and thus, neither device sees the full voltage potential between the power rail and the ground rail. Accordingly, the power clamp can function in voltage environments higher than the native voltage of the transistor devices. Additionally, the second transistor device is controlled by an RC network functioning as a trigger which allows the second transistor device to turn on during a voltage spike such as occurs during an ESD event. The capacitor of the RC network may be small thereby requiring small real estate on the integrated circuit. The clamp may have fast turn-on times as well as conducting current for long periods of time after turning on.
    • 为静电放电电源钳提供一种用于高压电源的结构和装置。 功率钳包括晶体管器件网络,例如串联布置在电源轨和接地轨之间的nFET。 第一晶体管器件被偏置成部分导通状态,因此,两个器件都不会看到电源轨和接地轨之间的全电压电位。 因此,功率钳可以在高于晶体管器件的天然电压的电压环境中工作。 此外,第二晶体管器件由用作触发器的RC网络来控制,该RC网络允许第二晶体管器件在诸如在ESD事件期间发生的电压尖峰期间导通。 RC网络的电容器可能很小,从而在集成电路上需要小的空间。 打开后,夹具可能会导通快速导通时间,并长时间传导电流。
    • 5. 发明申请
    • MULTILAYER SILICON OVER INSULATOR DEVICE
    • 多层硅绝缘体器件
    • US20080108185A1
    • 2008-05-08
    • US11961356
    • 2007-12-20
    • Mahmoud MousaChristopher Putnam
    • Mahmoud MousaChristopher Putnam
    • H01L21/84
    • H01L25/0657H01L25/18H01L2224/16H01L2225/06513Y10S257/903
    • An apparatus and method for a multilayer silicon over insulator (SOI) device is provided. In the multilayer SOI device, the crystal orientation of at least one active region of a device is different than the active region of at least another device. Where the multilayer SOI device has a first layer including a PMOS device with a silicon active region having a crystal orientation of [100], the second layer may be an NMOS device with a active region having a silicon layer having a crystal orientation of [110]. The second layer is bonded to the first layer. The method and apparatus can be extended to more than two layers thus forming a multilayer SOI device having a different crystal orientation at each layer. The multiple layer SOI device may form circuits of reduced surface area.
    • 提供了一种用于多层硅绝缘体(SOI)器件的设备和方法。 在多层SOI器件中,器件的至少一个有源区域的晶体取向与至少另一器件的有源区域不同。 在多层SOI器件具有包括具有[100]晶体取向的硅有源区的PMOS器件的第一层的情况下,第二层可以是具有晶体取向为[110]的具有硅层的有源区的NMOS器件 ]。 第二层结合到第一层。 该方法和装置可以扩展到两层以上,从而形成在每层具有不同晶体取向的多层SOI器件。 多层SOI器件可形成表面积减小的电路。
    • 6. 发明申请
    • MULTILAYER SILICON OVER INSULATOR DEVICE
    • 多层硅绝缘体器件
    • US20060043571A1
    • 2006-03-02
    • US10711167
    • 2004-08-30
    • Mahmoud MousaChristopher Putnam
    • Mahmoud MousaChristopher Putnam
    • H01L23/12
    • H01L25/0657H01L25/18H01L2224/16H01L2225/06513Y10S257/903
    • An apparatus and method for a multilayer silicon over insulator (SOI) device is provided. In the multilayer SOI device, the crystal orientation of at least one active region of a device is different than the active region of at least another device. Where the multilayer SOI device has a first layer including a PMOS device with a silicon active region having a crystal orientation of [100], the second layer may be an NMOS device with a active region having a silicon layer having a crystal orientation of [110]. The second layer is bonded to the first layer. The method and apparatus can be extended to more than two layers thus forming a multilayer SOI device having a different crystal orientation at each layer. The multiple layer SOI device may form circuits of reduced surface area.
    • 提供了一种用于多层硅绝缘体(SOI)器件的设备和方法。 在多层SOI器件中,器件的至少一个有源区域的晶体取向与至少另一器件的有源区域不同。 在多层SOI器件具有包括具有[100]晶体取向的硅有源区的PMOS器件的第一层的情况下,第二层可以是具有晶体取向为[110]的具有硅层的有源区的NMOS器件 ]。 第二层结合到第一层。 该方法和装置可以扩展到两层以上,从而形成在每层具有不同晶体取向的多层SOI器件。 多层SOI器件可形成表面积减小的电路。