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1. 发明授权

US5933026A Self-configuring interface architecture on flash memories 失效
标题翻译：闪存上的自配置接口架构
公开(公告)号：US5933026A
公开(公告)日：1999-08-03
申请号：US834026
申请日：1997-04-11
申请人： Robert E. Larsen , Harry Q. Pon , Sanjay Talreja , Marcus E. Landgraf , Ranjeet Alexis
发明人： Robert E. Larsen , Harry Q. Pon , Sanjay Talreja , Marcus E. Landgraf , Ranjeet Alexis
IPC分类号： G11C5/14 , G11C7/10 , H03K19/0185
CPC分类号： G11C7/1057 , G11C5/14 , G11C7/1051 , G11C7/1078 , H03K19/018585
摘要： A low-power interface for nonvolatile writeable memory is described. The interface includes an input buffer and an output buffer. The input buffer receives input signals having one of a number of pairs of logic levels. The input buffer is coupled to the nonvolatile writeable memory and coupled to the same power supply as the nonvolatile writeable memory. The input buffer translates the input signals received to the signal level used by the nonvolatile writeable memory. The output buffer is coupled to the nonvolatile writeable memory and is coupled to a different power supply from the input buffer and the nonvolatile writeable memory. The output buffer translates the signals received from the nonvolatile writeable memory to the same signal levels as the input signal. The input buffer and output buffer utilize input/output signals having logic levels compatible with complementary metal-oxide semiconductor (CMOS) technology.
摘要翻译：描述了用于非易失性可写存储器的低功率接口。该接口包括一个输入缓冲区和一个输出缓冲区。输入缓冲器接收具有多对逻辑电平中的一个的输入信号。输入缓冲器耦合到非易失性可写存储器并且耦合到与非易失性可写存储器相同的电源。输入缓冲器将接收到的输入信号转换为由非易失性可写存储器使用的信号电平。输出缓冲器耦合到非易失性可写存储器，并且被耦合到来自输入缓冲器和非易失性可写存储器的不同电源。输出缓冲器将从非易失性可写存储器接收的信号转换为与输入信号相同的信号电平。输入缓冲器和输出缓冲器利用具有与互补金属氧化物半导体（CMOS）技术兼容的逻辑电平的输入/输出信号。

2. 发明授权

US6088264A Flash memory partitioning for read-while-write operation 失效
标题翻译：用于读写操作的闪存分区
公开(公告)号：US6088264A
公开(公告)日：2000-07-11
申请号：US2649
申请日：1998-01-05
申请人： Peter K. Hazen , Ranjeet Alexis , Robert E. Larsen , Charles W. Brown , Sanjay Talreja
发明人： Peter K. Hazen , Ranjeet Alexis , Robert E. Larsen , Charles W. Brown , Sanjay Talreja
IPC分类号： G11C16/02 , G11C16/10 , G11C16/26 , G11C16/04
CPC分类号： G11C16/10 , G11C16/26 , G11C2216/22
摘要： A method and apparatus for partitioning a flash memory device is provided. The flash memory device includes a plurality of partitions, each partition able to be read, written, or erased simultaneously with the other partitions.
摘要翻译：提供了一种用于分区闪速存储器件的方法和装置。闪存设备包括多个分区，每个分区能够与其他分区同时读取，写入或擦除。

3. 发明授权

US06260103B1 Read-while-write memory including fewer verify sense amplifiers than read sense amplifiers 失效
标题翻译：读写存储器包括读取读出放大器的验证读出放大器
公开(公告)号：US06260103B1
公开(公告)日：2001-07-10
申请号：US09002645
申请日：1998-01-05
申请人： Ranjeet Alexis , Robert E. Larsen
发明人： Ranjeet Alexis , Robert E. Larsen
IPC分类号： G06F1516
CPC分类号： G11C16/26 , G11C16/10 , G11C2216/22
摘要： A read-while-write memory device. The read-while-write memory device includes a read memory plane and a write memory plane. A first number of read sense amplifiers greater than one is coupled in parallel to the read memory plane in response to a memory read operation. A second number of verify sense amplifiers greater than zero and less than the first number is coupled to the write memory plane in response to one of a memory write or erase operation.
摘要翻译：读写时存储器件。读写时存储器件包括读存储器平面和写存储器平面。响应于存储器读取操作，大于1的读取读出放大器的第一数量与读取存储器平面并联耦合。响应于存储器写入或擦除操作中的一个，第二数量大于零且小于第一数量的验证读出放大器被耦合到写存储器平面。

4. 发明授权

US06182189B2 Method and apparatus for placing a memory in a read-while-write mode 失效
标题翻译：将存储器置于读写模式的方法和装置
公开(公告)号：US06182189B2
公开(公告)日：2001-01-30
申请号：US09002691
申请日：1998-01-05
申请人： Ranjeet Alexis , Peter K. Hazen , Charles W. Brown , Robert E. Larsen
发明人： Ranjeet Alexis , Peter K. Hazen , Charles W. Brown , Robert E. Larsen
IPC分类号： G06F1300
CPC分类号： G06F13/4243
摘要： An interface for a read-while-write memory. A memory device includes a single-chip memory array and an interface that is responsive to one or more commands to configure the memory array in a read-while-write configuration.
摘要翻译：读写时存储器的接口。存储器件包括单芯片存储器阵列和响应于一个或多个命令以配置读写配置的存储器阵列的接口。

5. 发明授权

US5623620A Special test modes for a page buffer shared resource in a memory device 失效
标题翻译：存储设备中页面缓冲区共享资源的特殊测试模式
公开(公告)号：US5623620A
公开(公告)日：1997-04-22
申请号：US85542
申请日：1993-06-30
申请人： Mickey L. Fandrich , Salim B. Fedel , Ranjeet Alexis , Mamun Rashid
发明人： Mickey L. Fandrich , Salim B. Fedel , Ranjeet Alexis , Mamun Rashid
IPC分类号： G01R31/3185 , G06F11/22 , G06F12/02 , G11C11/00 , G11C16/10 , G11C29/26 , G11C29/48
CPC分类号： G11C29/48 , G01R31/318516 , G06F12/0246 , G11C11/005 , G11C16/10 , G11C29/26 , G06F11/2273 , G06F2212/7203
摘要： A flash memory device having a page buffer circuit with special testing modes. The page buffer circuit comprises a plane A and a plane B, each comprising a static random access memory array. The page buffer circuit further comprises a mode control circuit that maps the plane A and the plane B as a contiguous extended memory space accessible over a host bus. The page buffer circuit also maps the plane A and the plane B as a control store for a flash array controller of the flash memory device.
摘要翻译：一种具有特殊测试模式的页面缓冲电路的闪存设备。页面缓冲电路包括平面A和平面B，每个平面包括静态随机存取存储器阵列。页面缓冲电路还包括模式控制电路，其将平面A和平面B映射为可通过主机总线访问的连续扩展存储器空间。页面缓冲电路还将平面A和平面B映射为闪存器件的闪存阵列控制器的控制存储器。

6. 发明授权

US5748939A Memory device with a central control bus and a control access register for translating an access request into an access cycle on the central control bus 失效
标题翻译：具有中央控制总线和控制访问寄存器的存储器件，用于将访问请求转换为中央控制总线上的访问周期
公开(公告)号：US5748939A
公开(公告)日：1998-05-05
申请号：US601652
申请日：1996-02-14
申请人： Rodney R. Rozman , Richard J. Durante , Mickey L. Fandrich , Ranjeet Alexis
发明人： Rodney R. Rozman , Richard J. Durante , Mickey L. Fandrich , Ranjeet Alexis
IPC分类号： G11C29/50 , G06F13/16 , G06F12/00
CPC分类号： G11C29/50 , G11C16/04
摘要： A memory device includes a cell array having a plurality of memory cells and a read/write circuit having circuitry for selecting, writing, and reading the memory cells according to a plurality of control signals. A control register circuit is provided that has at least one control register coupled to communicate over a central control bus. A control access circuit is provided that receives an access request targeted for the control register, and translates the access request into an access cycle on the central control bus. The access cycle loads the control register and causes the control register circuit to generate the control signals. The control access circuit receives the access request targeted for the control register from an array controller circuit that generates the access request to load the control register and generate the control signals according to a user command received over a host bus. The control register includes an address decode circuit, a function decode circuit, a master data latch, a slave data latch, and a read control circuit.
摘要翻译：存储器件包括具有多个存储单元的单元阵列和具有根据多个控制信号选择，写入和读取存储单元的电路的读/写电路。提供了控制寄存器电路，其具有耦合以通过中央控制总线通信的至少一个控制寄存器。提供控制访问电路，其接收针对控制寄存器的访问请求，并将访问请求转换为中央控制总线上的访问周期。访问周期加载控制寄存器，并使控制寄存器电路产生控制信号。控制访问电路从产生访问请求的阵列控制器电路接收控制寄存器的访问请求，以加载控制寄存器，并根据通过主机总线接收的用户命令生成控制信号。控制寄存器包括地址解码电路，功能解码电路，主数据锁存器，从属数据锁存器和读控制电路。

7. 发明授权

US5621686A Multiply and divide current mirror 失效
标题翻译：乘以分频电流镜
公开(公告)号：US5621686A
公开(公告)日：1997-04-15
申请号：US480797
申请日：1995-06-07
申请人： Ranjeet Alexis
发明人： Ranjeet Alexis
IPC分类号： G05F3/26 , G11C7/06 , G11C16/28 , G11C7/02
CPC分类号： G05F3/262 , G11C16/28 , G11C7/062
摘要： A current mirroring circuit including first and second field effect transistor devices connected in a current mirroring arrangement, a circuit for summing a first plurality of identical currents to provide current for the first field effect transistor device, a circuit for dividing the current from the second field effect transistor device into a second plurality of identical currents, and an output circuit connected to mirror any one of the second plurality of identical currents.
摘要翻译：一种电流镜像电路，包括以电流反射装置连接的第一和第二场效应晶体管器件，用于对第一多个相同电流求和以提供第一场效应晶体管器件的电流的电路，用于将电流与第二场效应晶体管器件进入第二多个相同的电流，以及输出电路，连接到镜像第二多个相同电流中的任何一个。

8. 发明授权

US5864231A Self-compensating geometry-adjusted current mirroring circuitry 失效
标题翻译：自补偿几何调整电流镜像电路
公开(公告)号：US5864231A
公开(公告)日：1999-01-26
申请号：US940693
申请日：1997-09-30
申请人： Ranjeet Alexis
发明人： Ranjeet Alexis
IPC分类号： G05F3/26 , G05F3/16
CPC分类号： G05F3/262
摘要： A self-compensating current mirroring circuit including first and second transistor devices respectively joined in the path of a current to be mirrored and the path of a mirrored current, the first transistor device being in circuit with a compensating transistor device, the sizes of the first and second transistor devices being such that the currents through the first and second transistor devices are maintained at identical levels during operation.
摘要翻译：一种自补偿电流镜电路，包括分别连接在要被镜像的电流的路径中的第一和第二晶体管器件以及镜像电流的路径，第一晶体管器件与补偿晶体管器件电路相连，第一并且第二晶体管器件使得在操作期间通过第一和第二晶体管器件的电流保持在相同的电平。

9. 发明授权

US5835927A Special test modes for a page buffer shared resource in a memory device 失效
标题翻译：存储设备中页面缓冲区共享资源的特殊测试模式
公开(公告)号：US5835927A
公开(公告)日：1998-11-10
申请号：US719583
申请日：1996-09-25
申请人： Mickey L. Fandrich , Salim B. Fedel , Ranjeet Alexis , Mamun Rashid
发明人： Mickey L. Fandrich , Salim B. Fedel , Ranjeet Alexis , Mamun Rashid
IPC分类号： G01R31/3185 , G06F11/22 , G06F12/02 , G11C11/00 , G11C16/10 , G11C29/26 , G11C29/48 , G06F12/00
CPC分类号： G11C29/48 , G01R31/318516 , G06F12/0246 , G11C11/005 , G11C16/10 , G11C29/26 , G06F11/2273 , G06F2212/7203
摘要： A flash memory device having a page buffer circuit with special testing modes. The page buffer circuit comprises a plane A and a plane B, each comprising a static random access memory array. The page buffer circuit further comprises a mode control circuit that maps the plane A and the plane B as a contiguous extended memory space accessible over a host bus. The page buffer circuit also maps the plane A and the plane B as a control store for a flash array controller of the flash memory device.
摘要翻译：一种具有特殊测试模式的页面缓冲电路的闪存设备。页面缓冲电路包括平面A和平面B，每个平面包括静态随机存取存储器阵列。页面缓冲电路还包括模式控制电路，其将平面A和平面B映射为可通过主机总线访问的连续扩展存储器空间。页面缓冲电路还将平面A和平面B映射为闪存器件的闪存阵列控制器的控制存储器。

10. 发明授权

US5640083A Method and apparatus for improving power up time of flash eeprom memory arrays 失效
标题翻译：用于改善闪存存储阵列的上电时间的方法和装置
公开(公告)号：US5640083A
公开(公告)日：1997-06-17
申请号：US458805
申请日：1995-06-02
申请人： Ranjeet Alexis
发明人： Ranjeet Alexis
IPC分类号： G05F3/26 , G11C5/14 , G11C16/30 , G05F3/16
CPC分类号： G05F3/262 , G11C16/30 , G11C5/147
摘要： A circuit for rapidly raising the value of voltage at a circuit node to a predetermined precise level including first and second charging circuits, and circuitry including a timing circuit responsive to an enabling signal for connecting the one of the charging circuits to the circuit node for a first limited period and then connecting the other of the charging circuits to the circuit node thereafter.
摘要翻译：一种用于将电路节点处的电压值快速提高到包括第一充电电路和第二充电电路的预定精确电平的电路，以及包括定时电路的电路，该定时电路响应用于将一个充电电路连接到电路节点的使能信号，然后将另一个充电电路连接到电路节点。

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