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1. 发明申请

US20100067280A1 CHARGE MAPPING MEMORY ARRAY FORMED OF MATERIALS WITH MUTABLE ELECTRICAL CHARACTERISTICS 有权
公开(公告)号：US20100067280A1
公开(公告)日：2010-03-18
申请号：US12622308
申请日：2009-11-19
申请人： William S. Wong , Sanjiv Sambandan , Tse Nga Ng , Robert A. Street
发明人： William S. Wong , Sanjiv Sambandan , Tse Nga Ng , Robert A. Street
IPC分类号： G11C5/06
CPC分类号： G11C13/003 , B82Y10/00 , G11C11/22 , G11C13/0014 , G11C13/0016 , G11C2213/53 , G11C2213/74 , G11C2213/79 , G11C2213/80
摘要： A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic.A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.

2. 发明授权

US07425734B2 Thin-film transistor array with ring geometry 有权
公开(公告)号：US07425734B2
公开(公告)日：2008-09-16
申请号：US11190178
申请日：2005-07-25
申请人： William S. Wong , Jeng Ping Lu , Alberto Salleo , Michael L. Chabinyc , Raj B. Apte , Robert A. Street
发明人： William S. Wong , Jeng Ping Lu , Alberto Salleo , Michael L. Chabinyc , Raj B. Apte , Robert A. Street
IPC分类号： H01L27/148
CPC分类号： H01L27/283 , H01L27/12 , H01L27/3262 , H01L27/3274 , H01L29/41733 , H01L29/78696 , H01L51/0541 , H01L51/0545
摘要： An improved transistor array for a display or sensor device is described. The display or sensor device includes a plurality of pixels. Each pixel includes a width and a length. Each pixel is addressed by a transistor. The transistor addressing each pixel has a channel with a channel width. Each channel width is greater than the width or length of the pixel being addressed. By fabricating transistors with extremely long channel widths, lower mobility semiconductor materials can easily be used to fabricate the display device.

3. 发明授权

US07410882B2 Method of manufacturing and structure of polycrystalline semiconductor thin-film heterostructures on dissimilar substrates 有权
标题翻译：在不同基板上制造多晶半导体薄膜异质结构的方法
公开(公告)号：US07410882B2
公开(公告)日：2008-08-12
申请号：US10950452
申请日：2004-09-28
申请人： William S. Wong , Jeng-Ping Lu , Robert A. Street
发明人： William S. Wong , Jeng-Ping Lu , Robert A. Street
IPC分类号： H01L21/30
CPC分类号： H01L27/1266 , H01L21/76254 , H01L21/763 , H01L27/1214 , H01L27/1274 , H01L29/78603
摘要： According to various exemplary embodiments of this invention, a method of producing a semiconductor structure is provided that includes providing a layered structure on a first substrate, the layered structure including a silicon layer that is provided over a first dielectric layer, a first dielectric layer that is provided over an etch-stop layer, the etch-stop layer provided over a buffer layer, the buffer layer provided over a sacrificial layer, and a sacrificial layer provided over a first substrate. Moreover, various exemplary embodiments of the methods of this invention provide for a second substrate over the layered structure, separating the first substrate and the sacrificial layer from the buffer layer, separating the buffer layer and the etch-stop layer from the first dielectric layer and providing a drain electrode and a source electrode over the layered structure. Moreover, according to various exemplary embodiments of the devices of this invention, a transistor device is provided that includes a substrate, a gate electrode over the substrate, a laser recrystallized polycrystalline semiconductor layer over the gate electrode and a source electrode and a drain electrode over the laser recrystallized polycrystalline semiconductor. Finally, according to various exemplary embodiments of the devices of this invention, a transistor device is provided that includes a substrate, a laser recrystallized polycrystalline semiconductor over the substrate, a source electric and a drain electrode over the laser recrystallized polycrystalline semiconductor and a gate electrode over the source electrode and the drain electrode.
摘要翻译：根据本发明的各种示例性实施例，提供了一种制造半导体结构的方法，其包括在第一基板上提供分层结构，所述层状结构包括设置在第一介电层上的硅层，第一介电层，提供在蚀刻停止层上，在缓冲层上提供的蚀刻停止层，设置在牺牲层上的缓冲层以及设置在第一衬底上的牺牲层。此外，本发明方法的各种示例性实施例提供了层叠结构上的第二衬底，将第一衬底和牺牲层与缓冲层分离，将缓冲层和蚀刻停止层与第一介电层分离，以及在层状结构上设置漏电极和源电极。此外，根据本发明的装置的各种示例性实施例，提供了一种晶体管器件，其包括衬底，衬底上的栅电极，栅电极上的激光再结晶多晶半导体层，以及源电极和漏电极激光再结晶多晶半导体。最后，根据本发明的器件的各种示例性实施例，提供了一种晶体管器件，其包括衬底，衬底上的激光再结晶多晶半导体，激光再结晶多晶半导体上的源电极和漏电极以及栅电极在源电极和漏电极上。

4. 发明授权

US08492876B2 Geometry and design for conformal electronics 有权
标题翻译：适形电子学的几何和设计
公开(公告)号：US08492876B2
公开(公告)日：2013-07-23
申请号：US12253390
申请日：2008-10-17
申请人： William S. Wong , Brent S. Krusor , Robert A. Street
发明人： William S. Wong , Brent S. Krusor , Robert A. Street
IPC分类号： H01L29/06
CPC分类号： H05K3/0044 , G02F2201/56 , H01L27/14603 , H01L27/14692 , H01L27/14812 , H01L29/78603
摘要： A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to a three-dimensional structure, cutting the two-dimensional, flexible substrate, the cuts being located to allow the two-dimensional substrate to be shaped, the cuts having at least one stress relief feature, and shaping the two-dimensional, flexible substrate to form the three-dimensional structure, the stress relief features arranged to alleviate stress in the three-dimensional structure. A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to a three-dimensional structure, cutting the two-dimensional, flexible substrate, the cuts being arranged to as to increase a radius of curvature to meet a stress relief parameter when the substrate is shaped, and shaping the two-dimensional, flexible substrate to form the three-dimensional structure. A three-dimensional electronic device having an electronic device formed on a flexible substrate, the flexible substrate formed into a three-dimensional structure, wedged-shaped portions removed from the substrate to allow the substrate to be formed into the three-dimensional structure, and a stress relief feature arranged adjacent to the wedge-shaped portions.
摘要翻译：形成三维电子器件的方法包括在二维柔性基板上形成至少一个电子器件，该电子器件根据三维结构形成，切割二维柔性基片，切割被设置成允许二维基底成形，切口具有至少一个应力消除特征，并且成形二维柔性基底以形成三维结构，应力消除特征被设置为减轻二维基底中的应力三维结构。形成三维电子器件的方法包括在二维柔性基板上形成至少一个电子器件，该电子器件根据三维结构形成，切割二维柔性基片，切割被布置成当基底成形时增加曲率半径以满足应力消除参数，并且将二维柔性基底成形以形成三维结构。一种具有形成在柔性基板上的电子器件的三维电子器件，形成为三维结构的柔性衬底，从衬底移除楔形部分以使衬底形成三维结构;以及紧邻楔形部分布置的应力消除特征。

5. 发明授权

US08411075B2 Large area electronic sheet and pixel circuits with disordered semiconductors for sensor actuator interface 有权
标题翻译：用于传感器执行器接口的大面积电子薄片和具有无序半导体的像素电路
公开(公告)号：US08411075B2
公开(公告)日：2013-04-02
申请号：US12206690
申请日：2008-09-08
申请人： Sanjiv Sambandan , William S. Wong , Robert A. Street
发明人： Sanjiv Sambandan , William S. Wong , Robert A. Street
IPC分类号： G06F3/038 , G06G5/00
CPC分类号： G06F3/038
摘要： A pixel circuit including a first transistor; a second transistor, the first transistor and the second transistor serially coupled between a first power supply terminal and a second power supply terminal; and a first capacitor coupled between a gate of the first transistor and a gate of the second transistor, and an electronic sheet including the same.
摘要翻译：一种像素电路，包括第一晶体管; 第二晶体管，第一晶体管和第二晶体管，串联耦合在第一电源端子和第二电源端子之间; 以及耦合在所述第一晶体管的栅极和所述第二晶体管的栅极之间的第一电容器以及包括所述第一晶体管的电子薄片。

6. 发明授权

US07125495B2 Large area electronic device with high and low resolution patterned film features 有权
标题翻译：大面积电子设备具有高分辨率和低分辨率图案胶片功能
公开(公告)号：US07125495B2
公开(公告)日：2006-10-24
申请号：US11019037
申请日：2004-12-20
申请人： Robert A. Street , William S. Wong , Alberto Salleo , Michael L. Chabinyc
发明人： Robert A. Street , William S. Wong , Alberto Salleo , Michael L. Chabinyc
IPC分类号： G01D15/00
CPC分类号： H01L51/0004 , H01L51/0011 , H01L51/0021
摘要： Two different processing techniques are utilized to respectively form high resolution features and low resolution features in a critical layer of an electronic device, and in particular a large area electronic device. High resolution features are formed by soft lithography, and low resolution features are formed by jet-printing or using a jet-printed etch mask. Jet-printing is also used to stitch misaligned structures. Alignment marks are generated with the features to coordinate the various processing steps and to automatically control the stitching process. Thin-film transistors are formed by generating gate structures using a first jet-printed etch mask, forming source/drain electrodes using soft lithography, forming interconnect structures using a second jet-printed etch mask, and then depositing semiconductor material over the source/drain electrodes. Redundant structures are formed to further improve tolerance to misalignment, with non-optimally positioned structures removed (etched) during formation of the low resolution interconnect structures.
摘要翻译：利用两种不同的处理技术在电子设备的关键层，特别是大面积的电子设备中分别形成高分辨率特征和低分辨率特征。通过软光刻形成高分辨率特征，并且通过喷墨印刷或使用喷射印刷的蚀刻掩模形成低分辨率特征。喷墨印刷也用于缝合不对齐的结构。产生对准标记的特征是协调各种处理步骤并自动控制缝合过程。通过使用第一喷射印刷蚀刻掩模产生栅极结构来形成薄膜晶体管，使用软光刻形成源极/漏极，使用第二喷射印刷的蚀刻掩模形成互连结构，然后在源极/漏极上沉积半导体材料电极。形成冗余结构以进一步改善对未对准的容限，在形成低分辨率互连结构期间，非最佳定位的结构被去除（蚀刻）。

7. 发明授权

US06742884B2 Apparatus for printing etch masks using phase-change materials 失效
标题翻译：使用相变材料印刷蚀刻掩模的设备
公开(公告)号：US06742884B2
公开(公告)日：2004-06-01
申请号：US09838685
申请日：2001-04-19
申请人： William S. Wong , Robert A. Street , Stephen D. White , Robert Matusiak , Raj B. Apte
发明人： William S. Wong , Robert A. Street , Stephen D. White , Robert Matusiak , Raj B. Apte
IPC分类号： E03F100
CPC分类号： B41J2/14008 , H01L21/0271 , H01L21/0332 , H01L21/0337
摘要： A method and system for masking a surface to be etched is described. A droplet source ejects droplets of a masking material for deposit on a thin-film or other substrate surface to be etched. The temperature of the thin-film or substrate surface is controlled such that the droplets rapidly freeze upon contact with the thin-film or substrate surface. The thin-film or substrate is then etched. After etching the masking material is removed.
摘要翻译：描述用于掩蔽待蚀刻表面的方法和系统。液滴源喷射掩模材料的液滴以沉积在待蚀刻的薄膜或其它衬底表面上。控制薄膜或基板表面的温度，使得液滴在与薄膜或基板表面接触时快速冷冻。然后蚀刻薄膜或衬底。蚀刻后，去除掩模材料。

8. 发明授权

US09035673B2 Method of in-process intralayer yield detection, interlayer shunt detection and correction 有权
标题翻译：过程中内部产量检测，层间分流检测和校正方法
公开(公告)号：US09035673B2
公开(公告)日：2015-05-19
申请号：US12693019
申请日：2010-01-25
申请人： Michael Yu Tak Young , Scott Jong Ho Limb , William S. Wong , Robert A. Street
发明人： Michael Yu Tak Young , Scott Jong Ho Limb , William S. Wong , Robert A. Street
IPC分类号： G01R31/14 , G11C29/02 , G01R31/28 , H01L21/66 , G11C29/04
CPC分类号： G11C29/025 , G01R31/2853 , G11C2029/0403 , H01L22/14 , H01L22/20
摘要： A system and method for in-process yield evaluation and correction in an array type of device are provided. The system and method include measuring electrical resistance between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad; and analyzing the measured electrical resistance to identify at least one of the following: GATE line open defects, GATE line bridge defects, DATA line open defects, DATA line bridge defects, and interlayer shunt defects.
摘要翻译：提供了一种用于阵列型设备中的过程中产量评估和校正的系统和方法。该系统和方法包括测量各个GATE线路，DATA线路，DATA总线I / O焊盘和GATE总线I / O焊盘之间的电阻; 并分析测量的电阻以识别以下至少之一：GATE线路开路缺陷，GATE线路桥梁缺陷，DATA线路开路缺陷，DATA线路桥梁缺陷和层间分流缺陷。

9. 发明申请

US20120164781A1 Disordered Nanowire Solar Cell 审中-公开
标题翻译：无序纳米线太阳能电池
公开(公告)号：US20120164781A1
公开(公告)日：2012-06-28
申请号：US13410224
申请日：2012-03-01
申请人： Robert A. Street , William S. Wong
发明人： Robert A. Street , William S. Wong
IPC分类号： H01L31/105 , H01L31/18
CPC分类号： H01L31/035227 , H01L31/075 , Y02E10/548
摘要： A disordered nanowire solar cell includes doped silicon nanowires disposed in a disordered nanowire mat, a thin (e.g., 50 nm) p-i-n coating layer formed on the surface of the silicon nanowires, and a conformal conductive layer disposed on the upper (e.g., n-doped) layer of the p-i-n coating layer. The disordered nanowire mat is grown from a seed layer using VLS processing at a high temperature (e.g., 450° C.), whereby the crystalline silicon nanowires assume a random interwoven pattern that enhances light scattering. Light scattered by the nanowires is absorbed by p-i-n layer, causing, e.g., electrons to pass along the nanowires to the first electrode layer, and holes to pass through the conformal conductive layer to an optional upper electrode layer. Fabrication of the disordered nanowire solar cell is large-area compatible.
摘要翻译：无序的纳米线太阳能电池包括设置在无序纳米线垫中的掺杂硅纳米线，形成在硅纳米线表面上的薄（例如50nm）的针涂层，以及设置在上层（例如，掺杂）层。无序纳米线垫在高温（例如450℃）下使用VLS处理从种子层生长，由此晶体硅纳米线呈现增强光散射的随机交织图案。由纳米线散射的光被p-i-n层吸收，导致例如电子沿着纳米线传递到第一电极层，并且空穴通过共形导电层到可选的上电极层。无序纳米线太阳能电池的制造是大面积兼容的。

10. 发明授权

US08198127B2 Charge mapping memory array formed of materials with mutable electrical characteristics 有权
标题翻译：电荷映射存储器阵列由具有可变电特性的材料形成
公开(公告)号：US08198127B2
公开(公告)日：2012-06-12
申请号：US12622210
申请日：2009-11-19
申请人： William S. Wong , Sanjiv Sambandan , Tse Nga Ng , Robert A. Street
发明人： William S. Wong , Sanjiv Sambandan , Tse Nga Ng , Robert A. Street
IPC分类号： H01L51/40
CPC分类号： G11C13/003 , B82Y10/00 , G11C11/22 , G11C13/0014 , G11C13/0016 , G11C2213/53 , G11C2213/74 , G11C2213/79 , G11C2213/80
摘要： A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic. A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.
摘要翻译：包括数据线的存储单元阵列; 电容器以及耦合在数据线和电容器之间的晶体管。电容器和晶体管中的至少一个包括具有可变电特性的材料。一种存储单元阵列，包括耦合在第一节点，第二节点和第三节点之间的第一晶体管; 以及耦合在所述第二节点和第四节点之间的第二晶体管。第一晶体管包括具有可变电特性的材料。

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