专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20180350430A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SYSTEM 审中-公开
公开(公告)号：US20180350430A1
公开(公告)日：2018-12-06
申请号：US16059255
申请日：2018-08-09
申请人： Renesas Electronics Corporation
发明人： Shigenobu KOMATSU , Masanao YAMAOKA , Noriaki MAEDA , Masao MORIMOTO , Yasuhisa SHIMAZAKI , Yasuyuki OKUMA , Toshiaki SANO
IPC分类号： G11C11/417 , H01L27/11 , G11C5/06 , G11C11/413 , G11C5/14 , H01L27/092
CPC分类号： G11C11/417 , G11C5/06 , G11C5/14 , G11C11/413 , H01L27/092 , H01L27/1104
摘要： A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

2. 发明申请

US20150049541A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20150049541A1
公开(公告)日：2015-02-19
申请号：US14484998
申请日：2014-09-12
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Masanao YAMAOKA , Kenichi OSADA , Kazumasa YANAGISAWA
IPC分类号： G11C11/417 , G11C5/14
CPC分类号： G11C11/417 , G11C5/14 , G11C5/148
摘要： When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.
摘要翻译：当降低构成晶体管的阈值电压以便在低电压下操作SRAM电路时，存在晶体管的漏电流增加的问题，结果是当SRAM电路不工作时的功耗同时存储数据增加。因此，提供了通过控制存储单元中的驱动器MOS晶体管的源极线ssl的电位来减小SRAM存储单元MC中的MOS晶体管的漏电流的技术。

3. 发明申请

US20170309327A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SYSTEM 审中-公开
公开(公告)号：US20170309327A1
公开(公告)日：2017-10-26
申请号：US15648702
申请日：2017-07-13
申请人： Renesas Electronics Corporation
发明人： Shigenobu KOMATSU , Masanao YAMAOKA , Noriaki MAEDA , Masao MORIMOTO , Yasuhisa SHIMAZAKI , Yasuyuki OKUMA , Toshiaki SANO
IPC分类号： G11C11/417 , G11C11/413 , G11C5/06 , G11C5/14 , H01L27/11 , H01L27/092
CPC分类号： G11C11/417 , G11C5/06 , G11C5/14 , G11C11/413 , H01L27/092 , H01L27/1104
摘要： A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

4. 发明申请

US20180158511A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
公开(公告)号：US20180158511A1
公开(公告)日：2018-06-07
申请号：US15887190
申请日：2018-02-02
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Masanao YAMAOKA , Kenichi OSADA , Kazumasa YANAGISAWA
IPC分类号： G11C11/417 , G11C5/14
CPC分类号： G11C11/417 , G11C5/14 , G11C5/148
摘要： When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.

5. 发明申请

US20160172022A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SYSTEM 有权
标题翻译：半导体集成电路设备与系统
公开(公告)号：US20160172022A1
公开(公告)日：2016-06-16
申请号：US15050074
申请日：2016-02-22
申请人： Renesas Electronics Corporation
发明人： Shigenobu KOMATSU , Masanao YAMAOKA , Noriaki MAEDA , Masao MORIMOTO , Yasuhisa SHIMAZAKI , Yasuyuki OKUMA , Toshiaki SANO
IPC分类号： G11C11/417
CPC分类号： G11C11/417 , G11C5/06 , G11C5/14 , G11C11/413 , H01L27/092 , H01L27/1104
摘要： A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.
摘要翻译：提供了可以对备用时的保留数据量的变化进行响应的半导体集成电路。半导体集成电路包括逻辑电路（逻辑）和多个SRAM模块。多个SRAM模块独立于逻辑电路进行功率控制，并且在多个SRAM模块之间执行独立的功率控制。具体地，每个SRAM模块的电位控制电路的一个端子和另一个端子分别耦合到单元阵列和本地电力线。一个SRAM模块的本地电源线和另一个SRAM模块的本地电源线共享一个共享的本地电源线。一个SRAM模块的电源开关和另一个SRAM模块的电源开关共同耦合到共享的本地电源线。

6. 发明申请

US20150380076A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：US20150380076A1
公开(公告)日：2015-12-31
申请号：US14835127
申请日：2015-08-25
申请人： Renesas Electronics Corporation
发明人： Noriaki MAEDA , Yoshihiro SHINOZAKI , Masanao YAMAOKA , Yasuhisa SHIMAZAKI , Masanori ISODA , Koji NII
IPC分类号： G11C11/412
CPC分类号： G11C11/412 , G11C5/063 , G11C5/14 , G11C11/419 , H01L27/11 , H01L27/1104
摘要： The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.
摘要翻译：本发明提供了一种具有SRAM的半导体集成电路器件，其满足对具有低电源电压的SNM和写入裕度两者的要求。半导体集成电路装置包括：与多个字线和多个互补位线对应地设置的多个静态存储单元; 多个存储单元电源线，其各自向连接到多个互补位线的多个存储器单元中的每一个提供工作电压; 多个电源电路由电阻单元构成，每个电阻单元各自向存储单元电源线提供电源电压; 以及预充电电路，其向互补位线提供与电源电压相对应的预充电电压，其中使存储单元电源线具有耦合电容，从而在相应的互补位线上传输写信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式